This paper presents a 3-D differential folded Hall sensor (HS) fabricated using standard 0.18-ìm CMOS technology; this HS includes 1-D folded lateral Hall sensor (FLHS) and 2-D folded vertical Hall sensor (FVHS). The proposed 3-D HS is laterally folded to reduce the effective conduction length and to decrease the offset voltage; a p+ guard ring is used to narrow the conducting channel and to improve magnetosensitivity. The magnetosensitivity is improved two-fold and the offset is eliminated using the differential topology. The proposed 1-D FLHS is sensitive to magnetic induction perpendicular to the chip plane BZ through the fast accumulation-slow release mechanism; the proposed 2-D FVHS is responsive to magnetic induction parallel to the chip plane, BX and BY, based on the interaction between the magnetoresistor (MR) and magnetotransistor, where MR is more dominant. Notably, the proposed 3-D HS operates with a small offset voltage of 0.26 mV and without magnetic hysteresis. For 2-D FVHS, at a voltage gain of 89.6 dB, the maximum sensor output ΔVH is approximately 196.4 mV at the applied magnetic induction of 5 mT and the maximum supply-current-related sensitivity SRI is approximately 5943 V/A·T at a current consumption of 6.25 mA for x- or y-channel. For 1-D FLHS, the maximum ΔVH is approximately 470.8 mV at 5 mT and the maximum SRI is approximately 14790 V/A·T at a bias current of 6.25 mA for z-channel. The magntosensitivity SRI of 1-D FLHS is approximately 2.35 times that of 2-D FVHS. The designed 1-D FLHS is a comparable to the performance of other publications. However, it experiences a high nonlinearity error in output Hall voltage at a low bias current. By contrast, the proposed 1-D FLHS has a linear performance in output Hall voltage at a high bias current.