This paper presents the design of a synergistic arithmetic logic unit (SALU) that combines a complementary metal-oxide–semiconductor (CMOS) and memristors using the modified gate diffusion input (m_GDI) technique. The proposed design aims to reduce power consumption, delay, and the number of transistors, which are critical parameters in digital VLSI design. We have incorporated the m_GDI technique to implement the SALU, resulting in a lower number of transistors and reduced power consumption along with the delay and power delay product (PDP). The whole proposed architecture has been constructed using a basic m_GDI cell that consists of one p-type (pMOS) and two memristors. Combinational arithmetic circuits like full adder and full subtractor have been designed using the XOR-based m_GDI approach, and their performance will double that of current methods. A 1-to-8 de multiplexer circuit has also been utilized to perform 8 different operations for the ALU. Using Cadence Virtuoso tools in 45-nm technology, we have simulated the proposed design and evaluated its performance with existing designs. The proposed design has the potential to be a viable option for low-power and high-performance digital VLSI design applications. It delivers improved power, delay, and PDP characteristics while using fewer components. The power consumption, delay, and PDP of the proposed architecture are 9.71E−6 W, 2.141E−9 s, and 2.0789E−14 J, respectively. Furthermore, the design comprises just 33 pMOS transistors and 66 memristors, which is a lower count and unique combination in contrast to previous techniques.