The paper describes the architectures of various subranging flash analog-to-digital converters (ADCs) along with the proposal of a novel subranging algorithm. A comparative study of the state-of-the-art designs are made with respect to the figure of merit (FoM) and excess delay (EXD) parameter. Simulations are carried out in generic process design kit (GPDK) 45-nm technology in SPECTRE environment. The proposed subranging ADC shows an overall improvement of power by 94% per conversion cycle as compared to flash ADC. The EXD of proposed subranging ADC shows an improvement by 74% compared to binary flash ADC but however is slower than flash ADC by 34%.