Resource-constrained Internet of Things (IoT) edge devices demand lightweight, energy efficient, and secure cipher designs with CMOS technology scaling to enhance hardware security. This work proposes and demonstrates for the first time the potential and challenges of using NCFETs for energy efficient and secure S-box design used in lightweight ciphers exploring the Feistel network structure at VDD = 0.5 V. Performance benchmarking is performed for the proposed NCFET-based S-box design of a Feistel network SLIM cipher with a baseline CMOS SLIM cipher and other existing NCFET PRESENT Cipher with Substitution and Permutation (SPN) networks. The proposed NCFET S-box design exploits the unique steep slope device characteristics and increases non-linearity in power traces caused by the extra gate capacitance of the NCFETs along with the highly secure Feistel network structure to enhance overall energy efficiency and DPA attack resiliency. A thorough DPA resiliency analysis of the proposed S-box design with performance metrics such as SNR, MTD, and SPD performance comparison with the baseline CMOS design and other state-of-the-art S-box designs has been performed. Performance benchmarking of the proposed S-box design of an ultra-lightweight NCFET-based SLIM cipher design with an equivalent baseline CMOS design shows ~4.25× lower energy consumption, a 16× increase in the attacker effect ratio, a ~3.7× reduction in signal-to-noise ratio (SNR) values, a 16× increase in the minimum traces to disclosure (MTD) value, and a ~13.4× higher security power delay (SPD) value at VDD = 0.5 V.