In this paper, a 16-nm 1P9M FinFET technology is used to design a computing-in-memory architecture based on a 4-kb single-ended SRAM. The proposed 6T SRAM cell enables an energy-efficient architecture by eliminating the direct connection between the complementary bit line (BLB) and the storage node Q. An Ultra-low threshold voltage (ULVT) transistors in the 2T switch reduce the requirements for capacitors and current compensation circuitry. Additionally, ULVT transistors are integrated into the control circuits of both the SRAM core array and the CIM core, reducing delay caused by threshold voltage drops in the ultra-low supply voltage environment of the 16-nm technology node. The resulting architecture efficiently supports the core operations for convolutional neural networks (CNNs), including addition, signed multiplication, and logical functions. This work highlights the potential of SRAM-based CIM architectures that deliver an energy efficiency of 75.47 TOPS/W and an area efficiency of 140.25 GOPS/mm2 at a maximum operating frequency of 500 MHz.