Dr MD Najrul Islam, Assistant Professor in the Department of Electronics and Communication Engineering at SRM University-AP, along with a team of researchers, has published a groundbreaking research paper titled “Low-power Multi-Cauda Comparator Designed Using a Fragmentary Pre-charging Approach” in the prestigious IETE Journal of Research (2026).

The study introduces an innovative dynamic comparator architecture engineered for high-speed, energy-efficient Analog-to-Digital Converters (ADCs), solving a critical bottleneck in modern low-power electronics.

Understanding the Innovation: 

From smartphones and wearable devices to high-speed sensors and IoT hardware, modern technology relies heavily on Analog-to-Digital Converters (ADCs). ADCs translate real-world physical signals—such as sound, light, temperature, and radio frequencies—into digital signals (1s and 0s) that computer microprocessors can process.

At the heart of every ADC is a component called a comparator, which constantly evaluates incoming signals. However, traditional dynamic comparators consume significant battery power because they repeatedly charge and discharge their entire internal circuitry fully before making every single comparison.

To overcome this challenge, Dr Islam and his team developed a fragmentary pre-charging technique. Instead of fully charging the entire circuit during every cycle, the new design selectively pre-charges internal nodes only to a lower potential. This drastically reduces unnecessary switching activity and power consumption without sacrificing decision-making speed or sensitivity.

Key Technical Achievements

Implemented in 45-nm CMOS technology, the proposed 12-transistor comparator achieves remarkable performance benchmarks:

• Ultra-Low Energy Consumption: Operates at an average power consumption of just 367 nW and an energy metric of 9.27 fJ per conversion.
• High-Speed Performance: Achieves a maximum operating frequency of 2.5 GHz.
• High Precision: Maintains an input-referred offset voltage of 0.5 mV and kickback noise of 6.03 mV.

To validate its real-world effectiveness, the team integrated the comparator into a 10-bit flash ADC. The overall system delivered an impressive 2.5-GHz sampling frequency, an Effective Number of Bits (ENOB) of 8.51 bits, a Signal-to-Noise and Distortion Ratio (SNDR) of 53.05 dB, and 13.4 mW dynamic power consumption.

Practical Applications & Social Impact

By addressing the core trade-off between operating speed and power efficiency, this innovation holds significant potential for next-generation electronic and semiconductor systems. Key practical applications include:

• High-speed wireless communication devices (5G/6G systems)
• Portable, battery-powered electronics and IoT devices
• Low-power edge-computing hardware
• Medical and industrial sensor interfaces
• High-speed data acquisition equipment and signal-processing hardware

Future Research Directions

Building on these results, the research team aims to incorporate variable voltage thresholding to dynamically control the fragmentary pre-charging process based on real-time operating conditions. The long-term goal is to extend these ultra-low-power techniques to advanced ADC architectures powering edge computing, intelligent autonomous systems, and modern VLSI hardware.

Academic Collaborations

This research represents a successful multi-institutional collaboration uniting expertise across low-power VLSI design, mixed-signal circuits, and high-speed electronic systems.

The research team comprises Farhana Begum, Lachit Dutta, Md. Najrul Islam, Sandeep Mishra, Anup Dandapat, and Kandarpa Kumar Sarma, spanning key academic institutions in India.