Tunnel Transistor-Based Reliable and Energy Efficient Computing Architectures with Circuit and Architectural Co-Design at Low v DD Read More » December 24, 2025
Nano-scale Transistors with Circuit Interaction for Designing Energy-Efficient and Reliable Adder Cells at Low VDD Read More » December 24, 2025
Tunnel FET ambipolarity-based energy efficient and robust true random number generator against reverse engineering attacks Read More » December 24, 2025
Tunnel FET-based ultralow-power and hardware-secure circuit design considering p-i-n forward leakage Read More » December 24, 2025
Low area overhead DPA countermeasure exploiting tunnel transistor-based random number generator Read More » December 24, 2025
A 128Kb RAM design with capacitor-based offset compensation and double-diode based read assist circuits at low vDD Read More » December 24, 2025
Hardware Security Exploiting Post-CMOS Devices: Fundamental Device Characteristics, State-of-the-Art Countermeasures, Challenges and Roadmap Read More » December 24, 2025
Tunnel FET-based ultra-lightweight reconfigurable TRNG and PUF design for resource-constrained internet of things Read More » December 24, 2025
Negative capacitance FETs for energy efficient and hardware secure logic designs Read More » December 24, 2025
An Energy-Efficient Hybrid Tunnel FET based STT-MRAM Memory Cell Design at Low VDD Read More » December 24, 2025
