Device and circuit co-design robustness studies in the subthreshold logic for ultralow-power applications for 32 nm CMOS Read More » December 24, 2025
Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic Read More » December 24, 2025
Design and analysis of double-gate MOSFETs for ultra-low power radio frequency identification (RFID): Device and circuit co-design Read More » December 24, 2025
Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tiedindependent gate and symmetricasymmetric options Read More » December 24, 2025
Design and scalability of a memory array utilizing anchor-free nanoelectromechanical nonvolatile memory device Read More » December 24, 2025
Design optimization of pulsed-mode electromechanical nonvolatile memory Read More » December 24, 2025
Compact modeling of a generic double-gate MOSFET with gate-S/D underlap for subthreshold operation Read More » December 24, 2025
Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction Read More » December 24, 2025
