Design and Analysis of Heterojunction Tunneling Transistor (HETT) based Standard 6T SRAM Cell Read More » December 24, 2025
Low power silicon-on-insulator heterojunction tunneling transistor architectures analysis at device level Read More » December 24, 2025
Circuit level low power design, implementation and performance evaluation of different SRAM bit cell configurations operating at ultra-low voltage Read More » December 24, 2025
An 86 db gain 18.06 mVrms input-referred noise LNA for bio-medical applications Read More » December 24, 2025
Design, implementation and power analysis of low voltage heterojunction tunnel field effect transistor based basic 6T SRAM cell Read More » December 24, 2025
Gate oxide overlapped heterojunction tunneling transistor based low power SRAM cell topologies Read More » December 24, 2025
Device and Circuit Level Design, Characterization and Implementation of Low Power 7T SRAM Cell using Heterojunction Tunneling Transistors with Oxide Overlap Read More » December 24, 2025
A Novel Teeth Junction Less Gate All Around FET for Improving Electrical Characteristics Read More » December 24, 2025
