This paper reports various optimization aspects of an ambipolar silicon nanowire field-effect transistor with high-κ source-drain (S/D) spacer using coupled 3-D Technology Computer Aided Design numerical device simulations. The impact of variation in device features, such as spacer material type and length of spacer (Lsp), gate dielectric and its thickness (tox) and intergate distance (dG1G2) on vital performance parameters of the device, such as ION, ION/IOFF, Subthreshold swing (S/S), Vt, and gm/Id, is investigated and analyzed. It is observed that increasing the spacer length increases Band to band tunneling rate probability through the thin barriers at ON-state. Moreover, the permittivity of spacer material is found to be closely related to the lateral fringe lines emanated from gate, resulting in a boosted ION as well as gm/Id at higher κsp. Scaling down the thickness of gate oxide is not found to be a good idea, as it causes a reduction in ON-OFF current ratio though S/S remains mostly unaffected. However, intergate distance scaling is found to have a strong influence on device performance providing higher current drive and lower S/S for both n-and p-programs at lower dG1G2.