Background: The rapid improvement in technology enables design of high-speed devices, with development of modified computational elements for FPGA implementation. With complexity increasing day-to-day, there is demand for modified VLSI computational elements. Basically, for the past decade an improvement in basic VLSI Operators like Adder, multiplier is significant. The basic multiplication operator is been completely refined in the aspects of FPGA implementation. Materials and Methods: This paper presents a design of 32-bit high-speed MAC unit based on Vedic computations. Among the many sutras of Vedic mathematics, by using the urdhvatriyagbhyam sutra the products are generated in parallel. This proposed technique results in multiplication step reduction. Results: The result shows that the proposed MAC unit, the number of steps required for multiplication and addition has been reduced, it leads to the decrease in area size. In comparison with the performance of existing method to proposed MAC, the LUT’s are reduced by 50 percent. Conclusion: This paper comprehensively describes the basic Multiplication operation using urdhvatriyaghyam sutra for parallel multiplication process. Based on the Vedic sutras, the performance was analyzed on a hardware platform Spartan-3E Xilinx FPGA Device for a 32-bit MAC unit. The Implementation results shoes reduction in critical delay and area when compared to con-ventional booth multiplier-based MAC Design. Hence this works concludes that the proposed Vedic multiplier is suitable for constructing high speed MAC units.