In this paper, a quadral-duty digital pulse width modulation (QDPWM) control-based hardware accelerator for the auxiliary permanent magnet brushed DC (PMDC) motors of electric three-wheelers (E3Ws) is proposed. The proposed accelerator involves a precise motor speed calculation circuit, including a buffer to hold the position encoder signal for a predefined number of clock cycles to eliminate encoder signal noise. The proposed hardware accelerator is described with supporting mathematical models and is implemented on field-programmable gate array (FPGA) as well as application-specific integrated circuit (ASIC) platforms using SCL 180 nm CMOS technology library. The ASIC implementation at 12.5 MHz shows that the proposed design has significantly less area and power consumption than the conventional PI-PWM controller-based architecture and is comparable to the dual-duty digital pulse width modulation (DDPWM) controller. The proposed FPGA prototype-driven motor attains a wider speed range with low-speed ripple than DDPWM controller-based architecture. The position signal buffer circuit also enables the accelerator to tolerate noise or glitches in the position encoder signal, which makes the speed calculation precise and reliable. The proposed hardware accelerator-based PMDC drive performance has been validated regarding settling time, speed tracking ability, tolerance to dynamic speed, and load variations on a laboratory test setup.