The wearable gadgets facilitate the continuous real-time monitoring of personal health. The VLSI industry is attempting to incorporate more functional modules that run at high speed and consume less power inside the prescribed space. Several methodologies and procedures are designed to implement practical VLSI circuits to meet the market requirements. The Comparator is a basic arithmetic unit in high-end Processors for IoT-based applications. The concept of hybridization facilitates a promising solution to realize high-speed, low-power systems with a minimum number of transistors as compared to the CMOS technology. On the other hand, m-GDI-based logic circuit design is very popular for high-speed & low-power applications. These strategies demonstrate the trade-off between several parameters. In this paper, we have designed a novel CMOS-Memristors-based hybrid 16-bit magnitude compactor using the modified Gate Diffusion Input (m-GDI) technique. The proposed comparator operates at Vdd=1V and offers 12.71nw, 2.44ps, and 31.02zJ of power dissipation, delay, and PDP respectively. All the prescribed circuits have been designed and simulated using a 45nm Generic Process Design Kit (GPDK) in the Cadence Virtuoso tool.