This paper presents an energy-efficient multiplier architecture optimized for image processing applications. The proposed design modifies the traditional 4: 2 compressor within the partial product reduction stage to improve performance and reduce complexity. By introducing a new compressor structure, the multiplier achieves significant reductions in area, power consumption, and delay. The architecture was implemented and validated on an FPGA platform, demonstrating its practical effectiveness in real-time image multiplication tasks. Experimental results confirm that the proposed design offers substantial improvements in resource utilization and speed, making it a strong candidate for low-power, high-performance computing systems in error-resilient domains, proposed design has area efficient of 18% and power efficient of 5%.