In modern high-speed networking systems, the Ethernet MAC layer is essential for ensuring dependable and high-performance data transfer across network systems. This project presents the design and functional verification of an Ethernet MAC module, focusing on compliance with the IEEE 802. 3 standard. The verification environment was developed using SystemVerilog and Universal Verification Methodology (UVM), ensuring a modular, reusable, and scalable platform for constrained-random and coverage-driven verification. The environment incorporates key UVM components such as interface, transaction, driver, monitor, agent, scoreboard, and environment. A master-slave interface was created to facilitate MIIM (Management Interface) register access, supporting both read and write operations. To simulate physical layer communication, a PHY interface was implemented, and the MII (Media Independent Interface) was used to manage data exchange between the MAC and PHY layers. The testbench supported a range of test scenarios, including TX data path, RX data path, MIIM register write, MIIM register read, and PHY clock variation. Functional coverage metrics were captured to ensure verification completeness, and a scoreboard was employed for data comparison and result validation. This project delivers a robust and reusable verification environment tailored specifically for validating the Ethernet MAC design.