Singular Value Decomposition (SVD) is an elementary kernel in real-time signal processing, especially in Multiple-Input Multiple-Output (MIMO) communication systems. Conventional hardware implementations of the Brent & Luk Jacobi SVD algorithm are based on iterative CORDIC-based rotation blocks, which are known to have limitations in pipelining due to the dependency between rotation angle generation and matrix updating. In this paper, we propose a decoupled systolic array with an algebraic processing element to eliminate iterative rotation angle calculations through direct fixed-point implementations in DSP slices. A fully pipelined implementation is achieved with an initiation interval of 1. A polymorphic 32-bit fixed-point datapath supports both real and complex inputs and computes the singular values together with the corresponding orthogonal factors U and V without requiring conventional 2 N × 2 N structural expansion for complex matrices. The architecture also incorporates a permutation network to reduce data-movement overhead and an AXI4-Stream interface with zero padding to support matrices of arbitrary dimensions, including odd sizes. Implemented on a Xilinx Zynq UltraScale+ ZCU104 MPSoC, the design achieves operation at 250 MHz and reduces latency by up to 74.4% on a 20 × 20 matrix, while maintaining constant DSP and BRAM usage across tested matrix sizes.