This project primarily aims to design and validate the APB (Advanced Peripheral Bus) RAM using System Verilog by generating user defined testcases and transactions thereby obtaining cent percent functional coverage. The design is for providing simple, faster data rate, speedy read-write transactions, energy-efficient and budget-friendly approach for interfacing with low-speed peripherals like Real-Time Clock (RTC), Temperature Sensors, Watchdog Timers, Touchscreen Controllers, Light Sensors, Proximity Sensors, Keypad Interfaces, EEPROM by using APB protocol. This mechanism is intended to improve inter-chip communication and memory read/write efficiency. The proposed architecture is developed for communication between master and slave devices. Multiple read write transactions are implemented using multiple agents by making use of semaphore for selecting required agent based on semaphore keys. The memory simulation and verification is performed using the GVIM Editor and Questa Sim simulator. The test bench is further enhanced by implementing advanced features like concurrent task execution and comprehensive functional coverage analysis.