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Enhancing AES Security Through Simulated Power Trace Analysis and DPA Resistance

Year : 2025

Publisher : Institute of Electrical and Electronics Engineers Inc.

Source Title : OCIT 2025 - Proceedings 23rd OITS International Conference on Information Technology

Document Type :

Abstract

This research presents a simulated AES encryption and decryption system designed to protect against side-channel attacks using advanced masking and redundancy techniques. Two power trace generators were developed: one simulates power consumption with adjustable noise and scaling, and the other enhances security through masking and least significant bit (LSB) randomization. A Differential Power Analysis (DPA) attack model was used to test the system’s resistance by analyzing differences in power trace patterns. Implemented in Python, the simulation results show that the proposed system effectively hides power consumption behavior and significantly lowers the success rate of DPA attacks. By shuffling bits during each encryption round and spreading power usage across multiple paths, the system makes it harder for attackers to identify keyrelated activity. These countermeasures provide a strong defense compared to standard AES and show promise for future realworld and hardware-based cryptographic applications.