Device-Simulation-Based Machine Learning Technique and performance optimization of NSFET

Publications

Device-Simulation-Based Machine Learning Technique and performance optimization of NSFET

Year : 2024

Publisher : Institute of Electrical and Electronics Engineers Inc.

Source Title : Proceedings - 2024 OITS International Conference on Information Technology, OCIT 2024

Document Type :

Abstract

With the rapid growth of the semiconductor industry, it is clear that device simulation has been considered as slow process. As a result of semiconductor device downscaling, obtaining the inevitable device simulation data is significantly more expensive because it requires complex analysis of multiple factors. Using Machine Learning (ML) techniques to device modeling is promising, as their combination will lead to great outcomes in the semiconductor industry. Nanosheet Field Effect Transistor (NSFET) is a promising device for high-performance integrated circuits due to their superior electrical control and reduced short-channel effects. This paper presents a ML based Nanosheet Field Effect Transistor modeling. In traditional Technology Computer-Aided Design (TCAD) simulation, at once only a single simulation of NSFET for fixed length, width and thickness can be done, for change in any of the input parameter again simulation has to be done. To overcome this, simultaneous changes in input parameters are predicted using machine learning. The length, width, and thickness of the dielectric layer are input parameters and the drain current is the output parameter for the ML-based device model for NSFET. Experimental results have shown that our ML-based model can predict drain current accurately. R2-value is found be around 0.99832. The highest ION/IOFF ratio, very high ON current (ION), very low OFF current (IOFF) is achieved for NSFET. The primary goal of this work is to explore the possibility of ML model that can replace the device simulation to reduce the computational cost and drive energy-efficient devices.