Deploying Sparse Ternary Neural Networks on edge devices is in the areas of computational efficiency and energy optimization is a challenging task. This work presents a new FPGA-based accelerator integrating reinforcement learning and neural architecture search to dynamically optimize Sparse Ternary Neural Networks (Sparse TNN) for real-time applications. The design adopts adaptive pruning and quantization techniques for computational complexity and power consumption with the desired accuracy. Experimental evaluation on the Xilinx ZCU102 platform achieves up to 16.46 × speedup compared to dense models at less than 1% accuracy loss and achieves state-of-the-art performance on benchmarks such as Google Net and MobileNetV2. This work holds promise for resource-constrained high-throughput applications, bringing FPGA-based deep learning closer to efficiency and scalability.

In this paper, we present a detailed comparative performance analysis between MoS2 and WS2 2-D MOSFETs under varying temperature conditions. Although the WS2 device shows 68.55 µA/µm better on current at room temperature than the MOS2 one, the off-state leakage current is found to deteriorate in both cases with an increase in temperature mainly due to thermionic emission. Moreover, a lowering of Rch and better transconductance behaviour at higher temperatures is observed which is related to the predominant self-heating effect in these nanoscale SB devices. Lastly, it is seen that a thin gate oxide with a mediocre dielectric constant provides the best short-channel performance and device electrostatics for the two devices under consideration.

Solar energy is a renewable and eco-friendly alternative solution of fossil fuels (coal, gas and crude oil), providing an endless supply of energy. Solar cell is a semiconductor device which converts light energy into electrical energy, making them accessible and scalable for production. Quantum dots solar cell (QDSSC) has several advantages such as higher absorption coefficient, multiphoton generation, and tunable band gap. Most of the reported QDSSC device primarily focuses on narrow-band-gap semiconductor quantum dots like CdS, CdSe, PbS, CdTe and InAs. However, toxicity of Cd and Pb concerns make their use questionable for the practical uses. Graphene quantum dot (GQD) could be an alternative solution for the Cd and Pb based QDSSC. GQD is new kind of carbon-based nanomaterials has been utilizing in several application such as photodetector, solar cell, photocatalysis, bioimaging and chemical sensor. Here in, we have reviewed the synthesis of GQD, electronics, optical properties and the potential use of GQD for the application of quantum dots sensitized solar cell. Further current status and future scope of GQD as a quantum dot to replace the Cd and Pb based QD has been analyzed. Here, we propose a strategy to further improved the solar cell efficiency by up to 8%.

A first time comparative study of the thermal dependence of vital electrical characteristics of two-dimensional metal-oxide-semiconductor field-effect transistors based on black phosphorus for both zigzag and armchair orientations is presented in this paper. It is seen that a higher in-plane thermal conductivity in zigzag direction results in a much better on state current performance which comes at the cost of orders of magnitude increase in gate leakage and a reduced on to off state current ratio. The effect of temperature on threshold voltage (VTH), short channel effects like drain induced barrier lowering, subthreshold swing (SS), Schottky barrier height ΦSB and transconductance behavior in both zigzag and armchair orientations is thoroughly discussed and the inherent physical mechanisms resulting the variations are also presented. Though increase in temperature is found to deteriorate the SS and drain conductance but at the same time, it is found to improve the short channel performance of the devices under consideration.

This research investigates, for the first time, a novel eight-transistor-two-memristor (8T2M) nonvolatile static random access memory (NVSRAM) with 7-nm technology. The key innovation in this design lies in the incorporation of multiple-threshold complementary metal oxide semiconductor (MTCMOS) technology with power gating technique, which enables efficient power management and enhanced performance with low leakage current. The implementation of multiple threshold voltage levels allows for dynamic control of transistor behavior, optimizing power consumption and read/write speeds. As compared to a traditional six-transistor (6T) static random access memory (SRAM) cell, it has been ascertained that there is a 33% enhancement in the read margin and an 18% improvement in the write margin. Moreover, the delay for read, write ‘0’ and write ‘1’ is also minimized by 63.89%, 37.99% and 42.77%. Furthermore, the power attenuation is also reduced for read and write by 63.02% and 81.6%, respectively with respect to a conventional SRAM.

In this study, we investigate the performance and reliability of a novel static random-access memory (SRAM) cell utilizing advanced 5 nm FinFET technology. Our research aims to address critical challenges in SRAM design by integrating transmission gates and power gated transistors. Through extensive simulations using the Cadence Virtuoso tool, we optimize the SRAM cell’s read and write paths, resulting in substantial improvements in both functionalities. Additionally, our study unveils temperature-dependent variations in the read current and write margin, emphasizing the influence of temperature on SRAM performance. Compared to conventional FinFET SRAM circuits of equivalent bit-cell area and read latency, our innovative design showcases remarkable improvements across various parameters. Specifically, we achieve a commendable increase of 6.16% in the write static noise margin (WSNM) and 5.86% in the hold static noise margin (HSNM). Moreover, our findings reveal a substantial boost in read stability, increasing from 14.75% to 18.35%. These advancements underscore the promising potential of our approach in paving the way for future innovations in high-performance memory architectures. By leveraging state-of-the-art technology and meticulous optimization techniques, our research sets a new standard for SRAM design, offering enhanced performance, reliability, and efficiency in memory systems.

Semiconductor quantum dots such as CdSe, PbSe, PbS, CdS, CuInS, CuInSe, etc. have been extensively studied for their size-tunable optical absorption and emission properties, which enable their applications in different optoelectronics applications. Although despite having high photoaborption and photosensing properties these semiconductor quantum dots possess certain limitation due to their high level of toxicity and complex synthesis process. Graphene quantum dots (GQDs) are a zero-dimensional (0D) nontoxic nanomaterial of the carbon family, and have sparked a lot of attention in the domains of optoelectronics and electronics. In this review, a number of GQD synthesis methods such as laser ablation, hydrothermal, solvothermal, thermal pyrolysis, electrochemical, chemical oxidation and cutting have been summarized in detail.

Two Phase Clocked Adiabatic Static CMOS Logic (2PASCL) approach is proposed as an efficient power reduction technique in this work to reduce the overall power consumption of any VLSI circuit. One of the most significant area of research in today’s VLSI domain is power reduction. By using a complementary phase-shifted voltage source, we can minimize the charging-discharging of the load capacitor in each clock pulse, which plays a vital role in reducing the circuits’ dynamic power consumption.

A review of the electrical and physical characteristics of FinFETs is presented here. This work focuses on the latest structures of FinFET according to its classifications and three-dimensional schematics. Through studying the output I-V characteristics, the transfer characteristics, and the subthreshold current in the FinFET channel, the electrical characteristics of FinFETs have been analyzed. Considerations were made of coulomb, phonon, and surface roughness scattering to examine effective charge carrier mobility in the FinFET channel. Lastly, in this chapter, the impact of the Fin layer shape on device performance is studied.

This paper proposes a dual-material dual gate (DMDG) FiNFET architecture that shows superior electrostatic control over the conventional FiNFET and planar MOS devices. The difference in the work function of the used gate metals and improved electrostatic integrity provided by the high-κ spacers mainly led to the performance improvements. Moreover, the proposed DMDG structure explores the possibility of a symmetric FiNFET architecture which will be highly beneficial from circuit application point of view.

This paper explores source/drain (S/D) spacer technology-based reconfigurable field-effect transistors (RFETs) and a detailed physical insight toward the advantages of using spacer oxide in RFETs for applications involving rapid temperature fluctuations and reduction of circuit delay in contrast to conventional ambipolar FETs and other devices based on band-to-band tunneling (BTBT) such as TFETs. Temperature-based DC, analog and RF performance of gate-all-around (GAA), heterogeneous gate dielectric GAA, SiGe, and full silicon TFETs are compared. Moreover, it is also shown that the propagation delay in logic circuits is reduced for the proposed DG-RFET resulting in more robust and improved circuit performance.

In this paper, we have developed a physics-based compact model for surface potential and drain current for a dual gate source/drain (S/D) spacer-based silicon nanowire reconfigurable field-effect transistor (RFET). The models are derived by dividing the active region of the device into several portions based on positioning of the gates, spacers, and the metal-silicide Schottky junctions. A charge density expression is first developed and the quasi-fermi potentials for both electron and hole transport are found out by applying the principle of current continuity. Using these and further solving the 2-D Poisson's equation self consistently for various subregions of the device, the drain current and surface potential are modeled subsequently. The model includes the effects of drain voltage, nanowire radius, temperature and Schottky barrier height. The accuracy of the derived results is tested using 3-D numerical technology computer aided design simulations. The proposed model can be used to study the behavior of ambipolar FETs having S/D spacers for varying device dimensions and also can be utilized for the future design of memory devices and circuits using spacer-based RFETS.

This paper investigates for the first time the temperature dependence of the digital/analog parameters and RF figure of merits (FOMs) of a spacer based reconfigurable field-effect transistor (RFET) and compares the same with the existing RFET topology and other devices which depend on band-To-band tunneling (BTBT) for their on-current generation. It is observed that the output characteristics of the device are less sensitive to the temperature in the BTBT dominated on-state region as compared to the subthreshold one which is thermionic emission dependent. Having a better thermal stability over tunnel field effect transistor (TFET) and significantly lesser Vth roll-off, the proposed device portrays orders of magnitude reduction in parasitic gate capacitances and intrinsic delay as compared to gate-All-Around (GAA) and hetero gate dielectric GAA TFET devices over the considered range of temperature, thus assuring higher switching speed for digital applications. Moreover, superior analog/RF performance is also exhibited by the device under consideration for all temperatures in contrast to SiGe, full silicon TFETs, and conventional RFET topology owing to higher BTBT dominance and better gate controllability. Apart from all of these performance gains, the device FOMs are found to be less sensitive to temperature variations making it more suitable for applications where temperature fluctuation is a major concern.

The evolution of microelectronics industry is only possible through a combined effort of device miniaturization, innovative device structures and improved material property retaining the same functional efficiency. Out of several non-conventional device structures proposed in the literature, Tunneling Field Effect Transistor (TFET) is becoming a probable alternative device for future generation VLSI circuits due to its inherent feature of carrier conduction by the band to band tunneling mechanism. In the present work, a novel Gate All Around Schottky Junction (GAASJ) TFET with Highly Doped Pocket (HDP) and stacked gate oxide is proposed and investigated by Synopsys 3D TCAD. The device under consideration is having a Schottky Junction between Source made up of Nickel Silicide (NiSi2) and HDP which provides the steep tunneling width and improvises the device performance in terms of vital parameters such as ION, ION/IOFF and Subthreshold Slope (SS). The reported parameters of the proposed GAASJ TFET have shown improvement in the technological mode of TFETs with ION ∼10−5 A and SS ∼58.2 mV/decade. We have found 15x ION/IOFF for the GAASJ-HDP TFET over the conventional GAA TFET.

A reconfigurable field-effect transistor (RFET) with the ability to provide both n- and p-type characteristics with a single transistor is among the class of those emerging devices which show great promise to become the building block of future nanoelectronics. A comprehensive investigation using extensive 3-D device simulations on the effects of varying the gate-channel and spacer-channel underlap on the device characteristics of such a DG-RFET is reported for the first time in this paper. It is demonstrated that by appropriate designing of the gate- and spacer-channel underlap, the on-current and on-off current ratio of the device can be significantly improved. Moreover, it is also found that increasing the gate dielectric constant for a fixed equivalent oxide thickness improves its delay performance. Finally, we have also reported results related to the scaling properties of such a device.

This paper reports various optimization aspects of an ambipolar silicon nanowire field-effect transistor with high-κ source-drain (S/D) spacer using coupled 3-D Technology Computer Aided Design numerical device simulations. The impact of variation in device features, such as spacer material type and length of spacer (Lsp), gate dielectric and its thickness (tox) and intergate distance (dG1G2) on vital performance parameters of the device, such as ION, ION/IOFF, Subthreshold swing (S/S), Vt, and gm/Id, is investigated and analyzed. It is observed that increasing the spacer length increases Band to band tunneling rate probability through the thin barriers at ON-state. Moreover, the permittivity of spacer material is found to be closely related to the lateral fringe lines emanated from gate, resulting in a boosted ION as well as gm/Id at higher κsp. Scaling down the thickness of gate oxide is not found to be a good idea, as it causes a reduction in ON-OFF current ratio though S/S remains mostly unaffected. However, intergate distance scaling is found to have a strong influence on device performance providing higher current drive and lower S/S for both n-and p-programs at lower dG1G2.

In this letter, we optimize and investigate for the first time the effect of source/drain spacer oxide on the performance of a dual gate ambipolar silicon nanowire field effect transistor. Using extensive 3-D TCAD simulations, we show that the OFF-state leakage can be reduced by more than two orders of magnitude owing to the combined use of HfO<inf>2</inf> spacer and high-κ gate dielectric, resulting in an enhanced ON/OFF current ratio >10¹¹ for both n and p-FET as compared with reported values of ~10⁹. Comparing with the existing experimental dual and trigate ambipolar devices, 64.1% improvement in subthreshold slope for n-FET and 61.8% (40.9%) for n (p-FET) are observed. Having, an improvement in the ON-state current with J<inf>Dmax</inf> of 767.51 (263.05) kA/cm^-2 for n-FET (pFET), the device promises excellent ultra low power logic performance, with ambipolarity.

In this paper we propose a new structure of InxAl1-xN/GaN based HEMT with gate length of 20nm. The InAlN barrier layer is intentionally doped to boost the 'Figure of Merit'. We obtained an Ion/Ioff ratio of 1010.1 and found that it is 105 times better than the undoped barrier conventional InAlN/AlN HEMT. This excellent 'Figure of Merit' of the proposed HEMT leads to low gate leakage current and extremely low parasitic capacitances and conductance than the existing conventional InAlN/AlN HEMT. Further the RF and Microwave characteristics of this proposed HEMT is presented with the help of Stern stability factor, max transducer power gain and the RF parameters are presented by Smith chart and Polar plot.

HEMT as a microwave component has undergone a lot of experimentation for the last three decades since its invention at Bell labs by Takashi Mimura. InAlN has proved to be an extremely useful ternary semiconductor compound for its excellent scalability and high breakdown field[1] and turned out to be an ideal replacement for AlGaN as barrier for modern day HEMT's. In this paper we report a 20nm InAlN/AlN/GaN HEMT for which InAlN acts as donor as well as barrier layer. The barrier layer was intentionally doped to improve the current capability and we registered an ION/IOFF ratio of 1010.1 for our device and on comparison with the conventional InAlN/GaN HEMT having an undoped barrier we have seen that the proposed device have a 105 times better ION/IOFF ratio. In this paper we discuss about the 2DEG transport properties and mobility performance for the device under consideration.

We propose a new structure of InxAl1-xN/GaN high electron mobility transistor (HEMT) with gate length of 20 nm. The threshold voltage of this HEMT is achieved as -0.472 V. In this device the InAlN barrier layer is intentionally n-doped to boost the ION/IOFF ratio. The InAlN layer acts as donor barrier layer for this HEMT which exhibits an ION = 10-4.3 A and a very low IOFF = 10 -14.4 A resulting in an ION/IOFF ratio of 1010.1. We compared our obtained results with the conventional InAlN/GaN HEMT device having undoped barrier and found that the proposed device has almost 105 times better ION/IOFF ratio. Further, the mobility analysis in GaN channel of this proposed HEMT structure along with DC analysis, C-V and conductance characteristics by using small-signal analysis are also presented in this paper. Moreover, the shifts in threshold voltage by DIBL effect and gate leakage current in the proposed HEMT are also discussed. InAlN was chosen as the most preferred barrier layer as a replacement of AlGaN for its excellent thermal conductivity and very good scalability. © 2014 Chinese Institute of Electronics.

GaN and GaAs materials are the preferred materials of choice of worldwide researchers for High Electron Mobility Transistor (HEMT) due to suitable material properties. In this paper temperature dependence scattering effects are discussed. The degradation of mobility from different scattering mechanisms and its effect on drain current is also shown. The total mobility in bulk GaN and GaAs semiconductors are compared. The variations in electronic concentration with temperature are also presented in these types of HEMTs. The mobility degradation and its effect on drain current are also portrayed for AlGaAs/AlGaN HEMT’s.