Thermal noise plays a pivotal role in determining the high-frequency behavior and reliability of nanoscale transistors, particularly Gate-All-Around (GAA) nanowire MOSFETs. At such dimensions, this noise arises from intrinsic temperature-induced carrier fluctuations and structural imperfections, significantly impacting signal integrity. A common fabrication challenge at the nanoscale is achieving ideal geometries; deviations such as trapezoidal cross-sections with inclined sidewalls are frequently observed due to etching limitations. In this work, we examine how variations in sidewall inclination affect the thermal noise behavior of GAA nanowire transistors. Using thermally-aware simulation techniques, we systematically analyze the impact of sidewall angles (up to 20°) on key noise parameters, including channel thermal noise, induced gate noise, and gate-channel noise correlation. In addition, the sidewall inclination's effect along with the thermal contact resistance (Rtc) on thermal noise is explored. All the simulations have been carried out using the Sentaurus device simulator.

In this work, the design and performance analysis of a dielectric modulated N+ P+ I N+ P+ feedback field-effect transistor (FBFET) based label-free bio-sensor have been presented in detail. The extremely steep switching characteristics of FBFET enable the proposed biosensor to detect bio-molecules at higher sensitivity through positive feedback mechanism. We have introduced an intrinsic region of low-bandgap SiGe material between two channels of the device and created a cavity above this region to study biosensor performance. Sensitivity analysis has been performed on biomolecules with a wide permittivity (K) ranging from 1 to 22. The highest ON-drive current (ION), ON–OFF current ratio (ION/OFF), ON current sensitivity (SION), ON–OFF current sensitivity (SION/IOFF), best subthreshold swing parameter and the lowest threshold voltage (VTh) have been achieved as 7.7×10−5 A/μm, 2.81×1011, 5.87×102, 4.48×102, 0.036 mV/decade and 0.212 V respectively. In this study, the influence of biomolecule permittivity, positively and negatively charged biomolecules, cavity length and thickness, nano-cavity filling profile and filling factor, temperature, as well as the interface trap charge density on the performance metrics of the proposed device including ION, ION/OFF ratio, SION, SION/IOFF, and VTh have been analyzed in this study. The Sentaurus TCAD tool has been utilized to design the device and analyze its electrical characteristics.

This work presents, for the first time, the design and performance evaluation of a dielectric-modulated N+ P P+ N+ P+ vertical feedback FET-based label-free biosensor, demonstrating its potential for highly sensitive biomolecule detection. This work takes advantage of the superior characteristics of the vertical structure over the planar design, combined with the ultra-steep switching enabled by the positive feedback mechanism of the FBFET, resulting in a substantial enhancement in biosensor performance. Although FBFETs offer significant promise as ultra-steep switching devices capable of enabling highly sensitive sensors, research in this domain is still in its nascent stage. This study provides a detailed analysis of performance variations and sensitivities arising from factors such as the permittivity of different biomolecules, the presence of charged biomolecules, nano-cavity thickness, cavity filling profiles, the percentage of biomolecule filling and interface trap charge density. The ON current (ION), ON-OFF current ratio (ION/IOFF), threshold voltage (VTh), and subthreshold swing parameter (SS) of the proposed biosensor are 2.8×10−4 A/μm, 6.57×1010, 0.442 V, and 1.6×10−3 mV/decade, respectively, for K (dielectric constant of the biomolecule) = 22. The proposed biosensor achieves maximum sensitivities of 2139, 395, 0.79, and 0.997 for ION, ION/IOFF, VTh, and SS, respectively. The combination of high sensitivities and ultra-low SS enables the device’s efficient use in future low-power biosensor applications.

In this paper, we present a Deep Neural Network (DNN) to predict the current-voltage characteristics for feedback field-effect transistor (FBFET) devices. A Savitzky-Golay filter is used to remove noise from the output curve of the DNN and to make the transition in the predicted IV curve steeper. We fetch important device parameters like voltage threshold (Vth) and ON-current (Ion) with low deviation from actual values. We also compare the performance of DNN model with various regression models like Random Forest Regression (RFR) and Support Vector Regression (SVR) to demonstrate that our proposed model is superior to these methods. We train our model with a small data set of TCAD simulations and obtain high accuracy. Our work shows that a DNN along with a Savitzky-Golay filter can be used to understand sharp-switching device characteristics, even without a complete knowledge of the underlying physics. This can prove to be crucial for the design optimization of novel devices.

This work presents the design and performance analysis of a Si/SiGe superlattice-based double gate feedback field-effect transistor (SL DGFBFET). The proposed SL DGFBFET is designed successively by stacking 3 nm thin Si and Si1−x Gex layers to achieve a higher ON current, extremely steeper switching characteristics, and a larger memory window than Si-based DGFBFET. The device offers 19 times higher ON current (2.24 × 10−3 A/μm), 10.36 times higher ION/IOFF ratio (∼ 7.44 × 109), a large memory window of 1.7 V, and an extremely lower subthreshold swing (∼ 0.3 μV/decade) than a Si-based FBFET of similar dimensions with a molar fraction x = 0.4, which can be very useful for memory and neuromorphic applications. The device's OFF-to-ON switching is achieved at a lower gate voltage (threshold voltage = 0.34 V), making it suitable for low-power electronic devices. We have also shown the proposed device application in 1T DRAM which shows a remarkable performance in retention time (∼ 1000 s) and energy consumption (2.37 fJ/bit). The Synopsys TCAD tool has been utilized in the study to design the device structure and analyze its electrical performance.

This work presents the design and performance analysis of a tri-layered strained Si/Si1−xGex/Si heterostructure double gate feedback field-effect transistor (DG FBFET). The proposed DG FBFET is designed by introducing biaxial strain in the device by sandwiching a Si1−xGex layer between two thin Si layers to provide high ON current as well as ultra-steep switching characteristics. The device offers a significantly high ON current (3.4 x 10−3 A/μm), high I ON/I OFF ratio (∼1010), a large memory window of 1.06 V, and an extremely low subthreshold swing (∼0.3 μ V/decade), which can be very useful for memory and neuromorphic applications. Furthermore, the ON/OFF switching of the device has been accomplished at a lower threshold voltage (0.287 V), allowing it to be utilized in low-power electronics. Synopsys TCAD tool has been used to create the device structure and analyze the electrical performances of the device.

The design and performance analysis of a Si-SiGe heterostructure-based double gate feedback field-effect transistor (HDG FBFET) are presented in this paper. The proposed HDG FBFET is capable of providing high on current (3 × 10−4 A/μm) with a large I ON /I OFF ratio (3 × 1011) and is scalable up to 20 nm channel length. Its exceptionally steep switching characteristics (SS < 1 mV/decade) and ability to switch ON/OFF at lower gate voltage due to the use of smaller band-gap material (Si1−x Gex ) in channel-2 and drain regions make it suitable for use in low power applications. A significant hysteresis window of 4.99 V is also achieved by the device, which can be extremely helpful for memory applications. Moreover, a comprehensive investigation of the nature of hysteresis in relation to the different device parameters has also been carried out. The designing of the device structure and all of the electrical performance characterization have been done using the Sentaurus TCAD tool.

This paper proposes the structure of a vertical PNPN single gated feedback field-effect transistor (vertical FBFET) and investigates its performance using a TCAD simulator. The performance of the device is investigated against variations in a few geometrical and process parameters. The device exhibits an ultra-steep switching characteristic with a minimum subthreshold swing of 0.03 mV/dec and a high ON/OFF current ratio of ∼1011. Subsequently, the hysteresis characteristic of the vertical FBFET is analyzed against variation in interface trap charges at Si and Al2O3 interfaces. Due to the presence of negative/positive interface trap charges at silicon and Al2O3 interface, the memory window is enlarged/reduced from 1.1 V to 1.21 V/0.96 V respectively. The vertical FBFET also shows a wide variation in the memory window for channel length and temperature variations.