Development of trustworthy and secure hardware for Edge AI devices with increasing Deep Learning applications has gained recent attention. Logic locking has been a proven technology for secure and trustworthy designs for hardware obfuscation and enhanced protection of hardware against fault injection attacks (FIAs). Conventional CMOS based logic locking techniques result in increased overheads in respect of higher propagation delay and increased energy consumption due to the additional logic gates inserted for logic locking. This paper proposes a hardware methodology for obfuscation in a PRIDE S-box working at scaled supply voltages of VDD=0.5 V using a unique logic locking design with reduced energy consumption overhead using Negative Capacitance FET (NCFET). Further comparative performance of static complementary logic (SCL) vs pass transistor logic (PTL) designs with NCFETs for a robust and energy efficient PRIDE S-box has been explored and performance benchmarked. NCFET PTL based PRIDE S-box logic locked circuit design with an optimal tfe value (optimal tfe value ensures full logic swing for robust PTL design) achieves ∼61.62 % lower energy consumption when compared to NCFET based logic locking design using SCL. To demonstrate the enhanced hardware security and trustworthiness with NCFET PTL design, voltage-based fault injection attack (VFIA) has been performed and demonstrates ∼85 % error rate reduction compared to the equivalent baseline CMOS design.