Negative capacitance field effect transistor (NCFET) is a promising technology which exhibits lower subthreshold swing (SS) and high ON current beyond the limit of conventional CMOS. However, the lack of design insights and rules make NCFET circuit design challenging. To address this, proposed work discusses several design insights and advantages of NCFET based logic for energy efficient electronics. NCFET device demonstrates enhanced characteristics for logic design with ferroelectric layer thickness (t_{fe}) in the range of 3nm to 5nm. At 45nm technology node, NCFET with tfe of 5nm exhibits 1.22times higher ON current, 66times lower leakage current and a lower SS (50mV/dec) compared to baseline MOSFET. In addition, NCFET based static complementary inverter exhibited optimum performance with tfe of 3nm. At a supply voltage of 0.5V, NCFET inverter demonstrates 3.3times lower energy consumption compared to baseline inverter design. Furthermore, NCFET based logic gates (AND, OR, XOR) show at least 3times lower energy consumption compared to baseline designs at 0.5V.