Recent hardware developments in artificial intelligence (AI) edge devices expect architectures to support multiply and accumulation operations while preserving high inference accuracy and energy efficiency. This work proposes a compute in-memory (CiM) cell design with steep slope Negative capacitance field effect transistors (NCFET) for energy efficient computing architectures. The NCFET based 8T SRAM cell has been designed and analyzed for performance metrics such as noise margins and energy consumption during read/write modes for an optimum Ferroelectric layer thickness (Tfe) at VDD=0.3 V and 0.5V. Further, the NCFET 8T SRAM cell has been modified to realize energy efficient operations such as NCFET CiM based 2-input AND gate, NCFET CiM based 2-input XOR gate and NCFET CiM based half adder. Proposed NCFET CiM AND logic design exhibit ~5.85x lower energy consumption, NCFET CiM XOR logic design has ~3.29x lower energy consumption and NCFET CiM half adder logic design has ~6.57x lower energy consumption in comparison to equivalent baseline 40nm CMOS designs at VDD=0.5V.