Subthreshold logic has gained wide interest for ultra low power applications such as RFID, microsensors, energy harvesting etc. Double gate FinFETs are shown to be better candidates for subthreshold logic design than equivalent bulk devices, though it is not yet clear at this stage which configuration of DG-FinFETs will be more optimal for subthreshold logic. In this paper, we compare the different device and circuit level performance metrics of DG-FinFETs with different options for subthreshold logic. We observe that Energy Delay Product (EDP) shows to be a better subthreshold performance metric than PDP and the tied gate symmetric option has around 78% better EDP value than independent gate option. The asymmetry in oxide thickness further adds to reduction in EDP for tied gate and has no effect on independent gate option. The robustness of DG-FinFETs with different options has also been investigated in presence of parameter variations such as silicon body thickness, channel length, threshold voltage, supply voltage and temperature. Independent gate option has been seen to be more robust (≈40%) than tied gate option for subthreshold logic. ©2009 CODEC.