Designing high throughput and energy efficient CMOS transceivers for capacitive coupling interconnects in 3D ICs is a big challenge and involves trade-off. In this paper, steep slope characteristics of Tunnel FETs are exploited for designing energy efficient and high throughput transceivers for capacitive coupling mode interconnects. A TFET based transceiver design has been proposed taking the unique TFET device characteristics and the design achieves 26 GHz throughput and 0.33 pJ/bit energy consumption with pad dimension of 1.5×1.5 μm2 at 0.3 V.