A Negative capacitance field effect transistor (NCFET) based 6T SRAM based Computing-in memory (CIM) cell has been designed and explored for energy efficient demonstration of basic Deep neural networks (DNN) operation such as XNOR or Input and Weight product operation. The characteristics of NCFET devices have been explored to determine the optimal device performance window by varying the ferroelectric layer thickness of the device (Tfe) and it has been observed that the 40nm NCFET with a Tfe of lnm exhibits approximately 1.64x higher ON current, 1.1x lower leakage current and a Subthreshold swing of below 50mV/dec compared to the baseline MOSFET. Furthermore, NCFET based 6T SRAM CIM cell has been designed to perform basic XNOR operation at VDD = 0.3V and 0.5V. NCFET based CIM XNOR design has approximately 2.6x and 1.6x lower energy consumption compared to the equivalent baseline 40nm CMOS design at VDD = 0.3V and 0.5V respectively.