We propose a new analytical model to compute the potential distribution in gate overlap and underlap regions of a 3T- 4T double gate MOSFET valid for symmetric, asymmetric options for operation in the subthreshold condition. Conformai mapping technique has been applied for modeling fringing electric field in the underlap regions. The proposed model has been verified against reported models and a good agreement is found thus proving the accuracy of the proposed model. It has been observed that increasing the gate underlap region has significant effect on reducing short channel effects. The existing DGMOSFET potential models for subthreshold operation does not cover all 3T, 4T, asymmetric gate oxide thickness, asymmetric gate work functions and underlap region, which have been considered while model development. The developed model can be used for developing subthreshold current and slope models for underlap DGMOSFET with arbitrary gate biasing, gate insulator thickness and work functions. These models will simplify analyzing nano scale subthreshold logic circuits and system development of energy constrained applications such as RFID, wireless micro sensors and biomedical applications.