Tunnel FET based low voltage static vs dynamic logic families for energy efficiency Read More » December 24, 2025
Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SOCs Read More » December 24, 2025
Circuit and Architectural Co-design for Reliable Adder Cells with Steep Slope Tunnel Transistors for Energy Efficient Computing Read More » December 24, 2025
Tunnel transistors with circuit co-design in designing reliable logic gates for energy efficient computing Read More » December 24, 2025
Exploiting characteristics of steep slope tunnel transistors towards energy efficient and reliable buffer designs for IoT SoCS Read More » December 24, 2025
Low write energy STT-MRAM cell using 2T- hybrid tunnel FETs exploiting the steep slope and ambipolar characteristics Read More » December 24, 2025
Tunneling field effect transistors for energy efficient logic, sensor interface and 3D IC circuits for IoT platforms Read More » December 24, 2025
Exploiting the steep subthreshold slope characteristics of tunnel transistors for wide tuning range voltage controlled ring oscillator (VCRO) design at scaled supply voltages down to 150mV Read More » December 24, 2025
Robust and energy efficient non-volatile reconfigurable logic circuits with hybrid CMOS-MTJs Read More » December 24, 2025
Tunneling Field Effect Transistors for Enhancing Energy Efficiency and Hardware Security of IoT Platforms: Challenges and Opportunities Read More » December 24, 2025
