Three-dimensional integration suffers from heat dissipation between the layers due to the power consumed by various resources. In this paper, we show the significance of distribution of power density among the layers of a three-dimensional integrated circuit structure which can reduce the overall chip temperature as well as the peak temperature. Our experiments are developed using industry standard ANSYS tool and academic research tool HOTSPOT. Through the results obtained in this paper, we recommend that effective power density distribution at the early stage of design cycle, especially in the partitioning stage, will help in optimizing chip temperature and thus can reduce the burden on later stages of design cycle for handling critical design metrics.