Area scaling of 6T SRAM cells has stagnated in advanced technology nodes [1]. The conventional 6T SRAM bitcell is bulky because of two pull-down NMOSs, which are sized to ensure cell stability. In this work, we present alternative 4T SRAM and 6T SRAM cells that eliminate these pull-down transistors. A 4T SRAM cell, so designed, is 10-13% denser than a 6T bitcell. 4T SRAM cells typically suffer from low data retention time and need to be refreshed regularly. We apply Adaptive Body Bias to alleviate the retention problem. In 18nm FD-SOI technology, the retention problem is completely mitigated, and leakage is reduced by 6× times that of 6T SRAM cells.