The ring oscillator (RO) is widely used to address different hardware security issues. For example, the RO-based physical unclonable function (PUF) generates a secure and reliable key for the cryptographic application, and the RO-based aging sensor is used for the efficient detection of recycled ICs. In this paper, a CMOS inverter with two voltage control signals is used to design a configurable RO (CRO). With its control signals, the proposed CRO can both accelerate and lower the impact of aging on the oscillation frequency. This vital feature of the proposed CRO makes it suitable for use in PUFs and RO-based sensors. The performance of both the proposed modified architecture, i.e., CRO PUF and CRO sensor, is evaluated in 90 nm CMOS technology. The aging tolerant feature of the proposed CRO enhances the reliability of CRO PUF. Similarly, the aging acceleration property of CRO improves the rate of detection of recycled ICs. Finally, both the proposed architectures are area and power-efficient compared to standard architectures

This research paper investigates a hardware-type attack on System-on-Chips (SoCs) involving a trigger and a payload. A stealthy and controllable fabrication time attack, A2, is demonstrated, and a circuit is developed based on charge accumulation from rare events within the system. When voltage gets buildup due to charge coupling, the payload has been activated, leading to a privilege-escalation attack. In this research, a specific analog hardware Trojan (A2) detection and mitigation circuit is designed. This Trojan affects the circuit performance by targeting sensitive wires (like reset) in SoCs. This paper presents a method for detecting the Trojan and implementing proper mitigation techniques to safeguard SoCs from malicious attacks

Biometric authentication is pivotal in identifying individuals with unique physiological or behavioral characteristics. General recognition methods, such as fingerprint, voice, iris, and face recognition, are widely used but have significant flaws. These can be sensitive to spoofing, raise privacy concerns, and often struggle in certain environments. To fix these shortcomings, we proposed a novel biometric method: Electroencephalogram (EEG) authentication. Electroencephalogram (EEG) technology measures brainwave activity through electrodes and is known for its reliability, resistance to forgery, and inherent uniqueness, similar to fingerprints. EEG is particularly significant for liveness detection, making it a strong candidate for robust biometric authentication in high-security applications. This study utilizes a publicly available dataset consisting of EEG data from 109 subjects. The raw data is first scaled and then analyzed using various classifiers, such as ?-nearest neighbors (?-NN), Auto-Encoder with ?-NN, and Convolutional Neural Networks (CNN). The model's performance is evaluated under four different conditions based on the subjects' activities, with the CNN achieving an authentication accuracy of 92%.

A new promising hardware security primitive physically unclonable Function (PUF) is implemented to generate a unique secret key for each SOC Board. Especially FPGA-based, IoT is most widely used for different applications. Several types of PUFs are designed and implemented due to their remarkable performance for hardware security applications. In most of the PUFs ring oscillators are mostly preferred, but these are for limited input. In this context, we proposed a new PUF without increasing the size of the hardware implementation, and power. In this research, we used simple XNOR and XOR gates to increase the number of inputs. Even though it is a weak PUF, generally, weak PUFs is the most preferable for implementation, and by increasing CRPs, one can make a weak PUF as strong. This Arbitrary PUF is implemented on the Artix-7 AC701 Evaluation platform using Xilinx Vivado 2019.1.

Recently, harvesting natural energy is gaining more attention than other conventional approaches for sustainable IoT. System on chip power requirement for the internet of things (IoT) and generating higher voltages on chip is a massive challenge for on-chip peripherals and systems. In this article, an on-chip reliable energy-harvesting system (EHS) is designed for IoT with an inductor-free methodology. The control section monitors the computational load and the recharging of the battery/super-capacitor. An efficient maximum power point tracking algorithm is also used to avoid quiescent power consumption. The reliability of the proposed EHS is improved by using an aging tolerant ring oscillator. The effect of Trojan on the performance of energy-harvesting system is analyzed, and proper detection and mitigation mechanism is proposed. Finally, the proposed ripple mitigation techniques further improves the performance of the aging sensor. The proposed EHS is designed and simulated in CMOS 90-nm technology. The output voltage is in the range of 3-3.55 V with an input 1-1.5 V with a power throughput of 0-22 ?W. The EHS consumes power under the ultra-low-power requirements of IoT smart nodes.