This paper proposes implementation-friendly and dynamically reconfigurable VLSI-algorithm for convolutional neural network (CNN) inference engine. Based on this algorithm and additionally suggested techniques, high-throughput and hardware-efficient architecture of kernel processing unit (KPU) for the CNN inference engine has been presented here. It specially enables the proposed CNN inference-engine to achieve efficient local data reuse for all the computations of state-of-the-art CNN models. Hardware implementation of such KPU on Zynq UltraScale+ ZCU102 FPGA-board is capable of delivering 3.68× higher throughput and 3.40× higher energy-efficiency than the contemporary designs in the literature. Furthermore, this work suggests hardware-efficient architecture of classify unit for the CNN inference engine. It delivers 79.44% better hardware efficiency than the state-of-the-art work, when implemented on FPGA platform. In addition, aforementioned efficient-architectures of KPU and classify unit are aggregated to construct energy-efficient and high-throughput design of a complete CNN inference-engine. It has been FPGA implemented, and ASIC synthesized as well as post-layout simulated in 28 nm FD-SOI technology node. Hence, the suggested CNN inference engine with 864 processing elements delivers a peak throughput of 6.65 TOPs while operating at a maximum clock frequency of 3.85 GHz. To the best of authors' knowledge, such unified design and implementation of CNN inference engine (including both KPU and classify unit), which is specifically capable of supporting efficient reuse of local data for all computation while processing the state-of-the-art CNN models, has been reported for the first time in this paper. Finally, the proposed CNN inference engine has been functionally validated in the real-world test scenario for the object classification application, using contemporary CNN models.

This paper proposes simplified classification technique to reduce the complexity of softmax-based classification in the convolutional neural network (CNN) inference engine/accelerator. It primarily allows the CNN accelerator to directly classify the object from the activation of fully connected (FC) layer that avoids complex exponential and divisive operations. Corresponding to the suggested technique, this work also presents a hardware-efficient VLSI architecture of classify unit for CNN accelerator. Furthermore, the proposed classify-unit architecture has been ASIC synthesized and post-layout simulated in 28 nm-FDSOI technology node. As a result, our design delivers a peak throughput of 2.5 GIPS with a hardware efficiency of 5.05× 103 GIPS/mW/mm2. Comparison of these results with the relevant reported works indicates that the proposed classify unit manifests 24.1 × lesser area and 12.5× better hardware efficiency than the state-of-the-art implementations. Finally, complete CNN accelerator that is integrated with the proposed classify unit has been functionally validated with the aid of Zynq UltraScale+ ZCU102 FPGA-board in real-world scenario, using the MobileNet-V2 CNN model.

This article proposes an uninterrupted processing technique for the convolutional neural network (CNN) accelerator. It primarily allows the CNN accelerator to simultaneously perform both processing element (PE) operation and data fetching that reduces its latency and enhances the achievable throughput. Corresponding to the suggested technique, this work also presents a low latency VLSI-architecture of the CNN accelerator using the new random access line-buffer (RALB)-based design of PE array. Subsequently, the proposed CNN-accelerator architecture has been further optimized by reusing the local data in PE array, incurring better energy conservation. Our CNN accelerator has been hardware implemented on Zynq-UltraScale + MPSoC-ZCU102 FPGA board, and it operates at a maximum clock frequency of 340 MHz, consuming 4.11 W of total power. In addition, the suggested CNN accelerator with 864 PEs delivers a peak throughput of 587.52 GOPs and an adequate energy efficiency of 142.95 GOPs/W. Comparison of aforementioned implementation results with the literature has shown that our CNN accelerator delivers 33.42% higher throughput and 6.24 × better energy efficiency than the state-of-the-art work. Eventually, the field-programmable gate array (FPGA) prototype of the proposed CNN accelerator has been functionally validated using the real-world test setup for the detection of object from input image, using the GoogLeNet neural network.

In the current trend, deep neural network (DNN) models that use only one type of convolution filters (mostly 3×3 convolution) are widely adopted for the hardware implementation. However, inception-type convolutional neural network (CNN) model such as GoogLeNet showed that by combining different types of convolutions like 1 × 1, 3× 3, 7×7 etc., higher level of accuracy is achievable at the lower computational cost. This paper proposes first VLSI-architecture of a hardware accelerator for such GoogLeNet CNN models and a versatile CNN accelerator-architecture that is capable of performing three different types of convolution tasks with approximately equal hardware-efficiencies. This design of hardware accelerator has been synthesized and implemented on ZYNQ-102 Ultra-Scale+ FPGA-board with 16-bit brain-float quantization that consumes only 13.7k LUTs and delivers a throughput of 13.5 GFLOPS that makes our accelerator 16.45% more hardware efficient than the state-of-the-art implementations.

Successive-approximation-register (SAR) ADC has gained popularity owing to its low power consumption in the growing field of ADC development. This work describes such a structure through the use of a novel low offset comparator thereby reducing the non-linearity performance along with significant improvement in energy-delay metric. A high speed control circuitry is introduced to improve the overall frequency of operation of SAR-ADC minimizing its speed limitation. Capacitive based digital-to-analog converter is used that switches in alternate cycles to reduce the static power dissipation. The ADC architecture is designed in 45-nm CMOS technology at layout of 0.0139mm2. The extracted results show that the proposed design is a reliable framework to ascertain the effectiveness of SAR-ADC with a faster performance. The results demonstrate an improvement of 47.75% in figure-of-merit. SNDR and SFDR are found to be 57.2 dB and 61.4 dB respectively at input frequency of 10 MHz. The sampling frequency is taken as 1 GHz with a power supply of 1 V.

The paper describes the architectures of various subranging flash analog-to-digital converters (ADCs) along with the proposal of a novel subranging algorithm. A comparative study of the state-of-the-art designs are made with respect to the figure of merit (FoM) and excess delay (EXD) parameter. Simulations are carried out in generic process design kit (GPDK) 45-nm technology in SPECTRE environment. The proposed subranging ADC shows an overall improvement of power by 94% per conversion cycle as compared to flash ADC. The EXD of proposed subranging ADC shows an improvement by 74% compared to binary flash ADC but however is slower than flash ADC by 34%.