This study provides a comprehensive analysis of the impact of the interfacial properties on the performance of organic thin-film transistors (OTFTs) with a hybrid dielectric of Al2O3/PVP compared to single-layer dielectrics of Al2O3 and PVP. The analyses were performed using the 2D Silvaco Atlas numerical simulator, which conducted a detailed numerical investigation into how varying the thickness ratio of Al2O3 and PVP in the dielectric affects contact resistance and off-state current in short-channel OTFTs. High-K dielectric materials, such as Al2O3, offer low threshold voltages but lead to increased contact resistance and leakage current, while low-K dielectrics like PVP reduce leakage current but suffer from lower mobility and higher contact resistance. By utilizing a hybrid Al2O3/PVP dielectric, we successfully reduced the contact resistance to 4.84 KΩ.cm2, as extracted from VDS-ID characteristics at a gate voltage of -2V. Additionally, contact resistance significantly influenced the off-state current, particularly in devices of short channel length (1 μm). The PVP layer, with thicknesses ranging from 2.4 nm to 4.2 nm, effectively reduced charge carrier traps at the semiconductor/dielectric interface, enhancing mobility. Furthermore, hysteresis effects were examined through C-V characteristics by sweeping the gate voltage from -3V to +3V. These findings highlight the trade-offs in optimizing PVP thickness to balance interface quality and electrical performance in hybrid dielectric OTFTs.

This study analyses the vertically stacked GAA Multi-Bridge-Channel FETs like Nanosheet at the device level for CMOS applications. Studies are carried out to validate the impact of geometric deviations concerning thickness and width of the FET’s performance. The study also investigates the process parameter variation on DC metrics like threshold voltage (Vth), subthreshold swing (SS), ON-time (ION), OFF-time (IOFF), ION/IOFF, and DIBL. The device achieves better performance by optimizing Nanosheet width (NW) and thickness (NT) variability which ensures scaling flexibility. The CADENCE tool is used to investigate the device’s performance in terms of circuit applications. Various circuits like CMOS inverter transient response, switching characteristics, voltage transfer characteristics (VTC) and noise margins are evaluated. The CMOS inverter energy delay product (EDP) and power delay product (PDP) are also analyzed. The PDP and EDP increase by 2.51x and 3.06x with rise of NW. The CMOS inverter noise margins (NMs) are calculated towards digital circuit applications. The proposed Nanosheet FET has good electrostatic integrity due to its GAA structure, thus, it is a strong contender for low-power and high-performance applications for future technological nodes.

An innovative breakthrough that addresses the shortcomings of FinFET is the use of tree-shaped Nanosheet FET. This study examines the temperature dependence of the performance of 12 nm Tree-shaped NSFET on DC and analog/RF properties using a gate stack of high-k HfO2 and SiO2. From 200 K to 350 K, a detailed DC performance analysis was performed, including the transfer characteristics (ID vs VGS), output characteristics (ID versus VDS), subthreshold swing (SS), and ION/IOFF ratio. Additionally, we examined how temperature influence power consumption, dynamic power, and the ON-OFF performance metric (Q). Having the off current lesser than nA at all the temperatures, the proposed device shows good ION/IOFF switching performance. At an LG of 12 nm, the cutoff frequency (fT) is found to be in the Tera Hz region, and the Q varies from 0.9 to 5.1 μS-dec mV−1 at temperatures between 200 K and 350 K. Additionally, the impact of IB height (HIB) is investigated at 15-25 nm with the step of 5 nm and the impact of IB width (WIB) is investigated at 3-5 nm on Tree-shaped NSFET and the impact of variation in the work function is also done in this paper. The effect of scaling with different gate lengths from 20 nm down to 10 nm and its DC characteristics are examined in this paper. The power consumption of the Tree-shaped NSFET increases with temperature. From all these results, the proposed Tree-shaped NSFET shows great potential as a high-frequency competitor at the nanoscale.

Flexible and wearable electronics demand transistor technologies that can sustain stable performance under extreme mechanical deformation. In this work, we propose a quantitative benchmarking framework for strain resilience in organic thin-film transistors (OTFTs), introducing three normalized metrics: the Degradation Factor (DF), quantifying drain-current loss under strain; the Mobility Factor (MF), representing the rate of charge-transport degradation per unit strain; and the Strain-Stability Window (SSW), defining the maximum strain range within which devices remain in the safe operating zone (DF < 15%). Using Silvaco Victory TCAD, we systematically investigate the strain-dependent behaviour of single-dielectric (Al2O3) and hybrid-dielectric (Al2O3/PVP) OTFTs under both compressive (concave) and tensile (convex) bending with radii from 8 μm to 1 μm. Results show that hybrid dielectric OTFTs exhibit superior strain tolerance, with a degradation factor of only 9% under 9.85% tensile strain, compared to 25% for single-dielectric devices. Furthermore, hybrid devices show a markedly lower mobility factor (-3 %/strain compressive, -1.9 %/strain tensile) compared with single-dielectric OTFTs (-6 %/strain compressive, -5 %/strain tensile). Beyond confirming the mechanical advantages of hybrid dielectrics, our study demonstrates that strain-stability quantifiers provide a universal method to benchmark flexible OTFT reliability, bridging device physics with practical requirements of wearable bioelectronics. These findings establish hybrid Al2O3/PVP dielectrics not only as performance enhancers but also as reliable design enablers for next-generation strain-resilient organic electronics.

In this paper, a nanosheet field effect transistor (NSFET) which surrounds gate from all sides with two stack channels as a label free biosensor has been proposed and investigated by using visual TCAD tool. A nano-cavity (18 nm) is inserted between the channel and gate of nanosheet FET to immobilize the biomolecules. The electrical characteristics of the biosensor are examined in relation to various biomolecules, and it is found that the suggested biosensor is sensitive to both charged and neutral biomolecules. For each of the following materials, a change in current is noted as a result of a change in gate capacitance caused by a distinct biomolecule: (k =1), (k =2), (k =5), and (k=10). The threshold voltage (Vth), current switching ratio (Ion/Ioff), and subthreshold swing (SS) are used to study the sensitivity variation of biosensors to both charged and neutral biomolecules. For biomolecules (k=10), sensitivity is higher than for (k=1, 2, and 5).

This paper introduces a sub-1V output capacitorless low dropout regulator (OCL-LDO) for fast load transients. The OCL-LDO structures a multi-gain stage error amplifier and employs a dynamic transient enhancement (DTE) technique to improve response time. The proposed DTE significantly boosts the low-dropout (LDO) transient response by activating an additional biasing path at the power transistor’s gate during load transients. Moreover, it reduces the voltage undershoot and improves recovery time. Further aiding nested Miller compensation (NMC), an internal feed-forward circuit, and the Q-reduction concept in the fundamental multi-gain stage error amplifier contribute significantly to the LDO’s capacity to reject power noise at low frequencies and stabilize the output and guarantee consistent performance. The proposed design, fabricated using the 90nm CMOS process, works with a 1.1V supply voltage, delivers an output voltage of 0.9V, and consumes 26μA of quiescent current. There is a 150mV undershoot and a 180 ns settling period when the load-current increases from 5μA to 40mA with a risetime of 40 ns. Compared to an LDO without DTE, the suggested design shows better stability and driving capacity. Furthermore, the expected LDO achieves a measured PSR of 65dB at 10 kHz, demonstrating a notable improvement over the traditional system. According to the results of the trial, the suggested design results in a settling time that is around ten times faster and has less undershoot.

Various charged particles in space threaten memory circuit integrity and dependability, including photons, alpha particles, and high-energy ions outside the Low Earth Orbit region. These particles particularly affect conventional 6T SRAM by disrupting stored bits, leading researchers to explore radiation-hardened SRAM chips and the addition of extra nodes to memory cells to recover lost data. A novel self resilience radiation-hardened 14T (SRRH-14T) SRAM cell with redundant nodes is presented in this work to solve the soft error problem. The suggested SRRH-14T memory performance compared to well-known radiation-hardened cells, such as 6T-SRAM, Quatro-10T, SEA-14T, RH-14T, QCCS-12T, and RRS-14T. The proposed SRRH-14T memory cell applies to a minimal sensitive node layout area separation to protect against multiple node interruptions. Additionally, the proposed SRRH-14T demonstrates performance enhancements of 1.22x, 1.03x, 1.09x, 1.06x, and 1.02x relative to 6T-SRAM, Quatro-10T, SEA-14T, RH-14T, and RRS-14T, respectively.

The geometric design of electrodes plays a crucial role in determining the biosensor sensitivity and resolution by altering the Electric field (E). Specifically, the value of electric sensing parameters like resistance (R), capacitance (C), and impedance (Z), inherently depends on the strength of the generated electric field between electrodes. So, one must generate a large electric field for the applied AC or DC voltage. Unfortunately, the rigorous practical study on the same is limited on account of cleanroom-based fabrication techniques' cost and time. So, it is essential to study and analyze the geometrical performance of electrodes using simulations - present work aimed at this. In this work, we specifically selected gold-interdigitated microelectrodes (IDμEs) as one of the most viable alternatives to conventional two-electrode systems based on the enhanced field strength (E) generated for the same applied voltage. Specifically, the geometric study of gold IDμEs was carried out using the COMSOL Multiphysics simulator by varying the inter-finger distance and number of fingers between the electrodes. Based on the generated electrical field strength, one can select the best design for biosensor fabrication.

In the huge growth of semiconductor industry, it is noticed that the device simulation is a very sluggish process. It is very promising to use Machine Learning (ML) techniques in device modeling as their combination will create great results in semiconductor industry and reduce the computational time. Organic Thin Film Transistor (OTFT) is a promising alternative to amorphous silicon devices due to its flexibility, low cost, and can be manufactured at reduced temperatures. In traditional TCAD simulation, at once only a single simulation of OTFT for fixed length, width and dielectric thickness can be done, for change in any of the input parameter again simulation has to be done. To avoid this ML is used to predict drain current for simultaneous changes in input parameters. This introduces a machine learning based structure to model OTFT integrated with ML algorithm named Random Forest Regressor (RFR). ML based device model for p-type OTFT takes length, width and thickness of dielectric layer as input parameters and drain current as output parameter. Experimental results has shown that our ML-based model can predict drain current accurately. R2-value is found be around 0.997253. ML based performance optimization is a promising alternative to traditional technology computer aided design (TCAD) tools. The highest ION/IOFF ratio, very high ON current (ION), very low OFF current (IOFF) is achieved for OTFT. ION/IOFF ratio is obtained to be 1011. The trained RFR models can accelerate the optimization in terms of performance and serves as promising alternative.

With the rapid growth of the semiconductor industry, it is clear that device simulation has been considered as slow process. As a result of semiconductor device downscaling, obtaining the inevitable device simulation data is significantly more expensive because it requires complex analysis of multiple factors. Using Machine Learning (ML) techniques to device modeling is promising, as their combination will lead to great outcomes in the semiconductor industry. Nanosheet Field Effect Transistor (NSFET) is a promising device for high-performance integrated circuits due to their superior electrical control and reduced short-channel effects. This paper presents a ML based Nanosheet Field Effect Transistor modeling. In traditional Technology Computer-Aided Design (TCAD) simulation, at once only a single simulation of NSFET for fixed length, width and thickness can be done, for change in any of the input parameter again simulation has to be done. To overcome this, simultaneous changes in input parameters are predicted using machine learning. The length, width, and thickness of the dielectric layer are input parameters and the drain current is the output parameter for the ML-based device model for NSFET. Experimental results have shown that our ML-based model can predict drain current accurately. R2-value is found be around 0.99832. The highest ION/IOFF ratio, very high ON current (ION), very low OFF current (IOFF) is achieved for NSFET. The primary goal of this work is to explore the possibility of ML model that can replace the device simulation to reduce the computational cost and drive energy-efficient devices.

This research focuses on a quantum model created using an entirely novel nanosheet FET. The standard model describes the performance of a Gate-all-around (GAA) Junction-less (JL) nanosheet device with a gate dielectric of SiO2 and HfO2, each having a thickness of 1 nm. The performance of both the classical and quantum models of the GAA nanosheet device is evaluated using the visual TCAD tool, which measures the ION, IOFF, ION/ IOFF, threshold voltage, DIBL, gain parameters (gm, gd, Av), gate capacitance, and cut-off frequency (fT). The device is suited for applications needing rapid switching since it has a low gate capacitance of the order of 10-18, according to the simulation results. A transconductance (gm) value of 21 μS and an impressive cut-off frequency of 9.03 GHz are displayed during device analysis. A detailed investigation has also been done into the P-type device response for the same device. Finally, the proposed GAA nanosheet device is used in the inverter model. The NSFET-based inverter, although having higher gate capacitance, has the shortest propagation latency.

In this work, we report the RF/DC performance of novel AlN/GaN/Graded-AlGaN/GaN double-channel HEMT (AlN-GDC-HEMT) on SiC wafer for the first time. The study compares the performance between conventional AlGaN/GaN/Graded-AlGaN/GaN double-channel HEMT (AlGaN-GDC-HEMT) and the AlN-GDC-HEMT. Two quantum wells are formed in both devices, leading to distinct double peak features in transconductance and cut-off frequency plots, highlighting efficient inter-channel connection behavior. The study investigates the relative performance of AlN-GDC-HEMT and AlGaN-GDC-HEMT, exploring the influence of gate recess length (LR) and top barrier thickness. Additionally, the scaling behavior of the HEMTs is examined with varying gate lengths (LG). Furthermore, the impact of gate engineering and lateral scaling on both devices' DC/RF behavior is explored. Extensive comparative analysis shows that the AlN-GDC-HEMT outperforms the conventional AlGaN-GDC-HEMT, mainly attributed to AlN's higher polarization (spontaneous) density and its wider bandgap. The optimized AlN-GDC-HEMT with LG=40nm, LGS=250 nm, and LGD=400nm exhibits superior performance resulting in transconductance (G{M}}) values of 203.1 and 787.5 mS/mm at two peaks, an IDS_sat of 1.97 A/mm, IDS_sat of 3.18 A/mm, and the highest fT derived from the left and right peaks was 285.1 and 416.8 GHz, respectively. The promising results from this first investigation indicate the potential and applicability of AlN-GDC-HEMTs in future RF power amplifiers.

In this study, we propose a novel dielectric modulated dual-dielectric bottom-gate top-contact organic thin film transistor (DMDDBG-OTFT) as a label-free biosensor for detecting neutral and charged bio-analytes. The device utilizes PVP and Al2O3 as dual-dielectric layers, offering superior sensitivity, selectivity, low leakage current, and low operating voltage compared to single-layer dielectrics. A sensing cavity is formed by etching the oxide under the drain region and biomolecule detection is based on changes in the drain current due to dielectric modulation from variations in dielectric constants and charge densities. Electrical parameters, including ION/IOFF, subthreshold slope (SS), and threshold voltage (VTH), were computed using a 2D Silvaco Atlas simulator. The DMDDBG-OTFT showed over 78% higher drain current sensitivity than conventional OTFT biosensors, with sensitivity reaching 5.59 × 1011 for charged gelatin biomolecules (K =12), a low limit of detection (LoD) of 13% and high selectivity. Additionally, temperature analysis from 265-315 K confirmed thermal stability, making the device promising for flexible biosensing applications.

Wireless applications require a low power technology that enables DC/analog/RF functions on the same chip. It is well established fact that Multi-channel FinFET (Multifin) enhances the DC/analog/RF performance of the FET. The proposed design with spacer dielectric ensures reduced OFF current (IOFF), better subthreshold performance and improved ON current (ION) towards high performance and low power applications. Along with single-k spacer a dual-k spacer combination of (Air + Si3N4) called hybrid spacer (low-k towards gate and high-k near source/drain) is studied for the first time towards DC/analog/RF and linearity metrics of Multifin FET. The Air spacer shows extravagant performance towards RF domain and HfO2 shows better for DC and analog perspective. With Air spacer dielectric the Multifin FET exhibits terahertz (THz) frequency ranges and ensures high frequency applications. The linearity and harmonic distortion metrics towards wireless communication applications with various spacer dielectric is also analysed. The hybrid spacer shows better linearity and harmonic distortion performance along with Air and shows a strong contender towards RF applications. Moreover, the reduced capacitances ensure hybrid spacer is potential towards driving circuit applications at advanced nodes.

This study investigates the effect of polymer and inorganic dielectric materials on pentacene-based cylindrical organic thin-film transistors (C-OTFT). The gate dielectric has a significant impact on the design of C-OTFT. We performed a comparative investigation using the 3D-Atlas numerical simulator to analyze the electrical characteristics of C-OTFT on various gate dielectric materials, such as inorganic dielectric (S i O2) and organic dielectrics (PVP, PI). Our research revealed that differences in the dielectric constant and material properties of the dielectric layer led to deviations in performance metrics like threshold voltage, I on / I off ratio, capacitance, mobility, and subthreshold voltage swing. After that, an investigation showed that SiO2, an inorganic dielectric, works at low voltage, while organic dielectric materials have the highest field effect mobility and a steep subthreshold slope. The comparative analysis reveals that CTFT, using organic as the gate dielectric, outperforms S i O2 in mobility, making it a promising candidate for e-textile applications.

Tree-shaped Nanosheet FETS (NSFET) is the most dependable way to scale down the gate lengths deep. This paper investigates the 12nm gate length (LG) n-type Tree-shaped NSFET with the gate having a stack of high-k dielectric (HfO2) and SiO2 using different spacer materials, which can be done using TCAD simulations. The Tree-shaped NFET device with {mathrm {T}}_{mathrm {(NS)}} =5 nm, {mathrm {W}}_{mathrm {(NS)}} =25 nm, {mathrm {W}}_{mathrm {IB}} =5 nm, and {mathrm {H}}_{mathrm {IB}} =25 nm has high on-current (I_{ON} ) and low off-current (I_{OFF} ). The 3D device with single-k and dual-k spacers are compared and its DC characteristics are shown. It is noted that the dual-k device achieves the maximum I_{ON}/I_{OFF} ratio, which is 10^{9} , compared to 10^{7} because the fringing fields with spacer dielectric lengthen the effective gate length. Additionally, the impact of work function, interbridge height, width, gate lengths, and temperature, along with the device's analog/RF and DC metrics, is also investigated in this paper. Even at 12 nm LG, the proposed device exhibits good electrical properties with DIBL =23 mV/V and SS =62 mV/dec and switching ratio (I_{ON}/I_{OFF}) = 10^{9}. The device's performance confirms that Moore's law holds even for lower technology nodes, allowing for further scalability.

We discuss the probable replacement of FinFETs and gate-all-around (GAA) with nanosheet field effect transistor (NS-FET), which will continue to generate advantageous node to node scaling advantages. Improved electrostatics compared to FinFETs, gate-all-around and allowing for further gate length (Lgate) shrinkage, high design flexibility (a variety of NS widths are allowed), and larger drivability (ION) per layout footprint are all benefits of NS FETs, which increase the number of vertically stacked NS per device. The user is able to change the width of the sheet of the Nanosheet Field Effect Transistors in order to change the output currents (ID). it has an identical structure like Nanowire FET except the width is wider compared to nanowire FET, and can manage leakage current more effectively, which enhances high-power transistor performance. The greatest IONIOFF ratio, highest ON current (ION), lowest OFF current (IOFF), are all characteristics of the NS FET, which also has the higher subthreshold performance. With an ION/IOFF ratio of 109, a subthreshold slope (SS) of 62.5 mV/dec, and the threshold voltage of 0.37 V, the nanosheet FET attained the good electric properties. 3-D computer-aided design (TCAD) is used to simulate the nanosheet FET device. The analog and digital/RF performance of the device is also studied. The outcome shows the NSFET's enormous potential for forthcoming analog and digital circuit applications.

An approximate carry select adder (CSLA) with reverse carry propagation (RCSLA) is showed in this work. This RCSLA was designed with reverse carry propagate full adder (RCPFA). In RCPFA structure, the carry signal propagates in the reverse direction that is from MSB part to LSB part, then the carry input has greater importance compared to the output carry. Three types of implementations were designed in RCPFA based on the design parameters. This method was applied to RCA & CSLA to design other types of approximate adders. These designs and simulations were done in CADENCE Software tool with 45 nm COMS technology. The design parameters of the three CSLA implementations with RCPFA are compared with the existing CSLA adders.

The Editor-in-Chief and the publisher have retracted this article. The article was submitted to be part of a guest-edited issue. An investigation by the publisher found a number of articles, including this one, with a number of concerns, including but not limited to compromised editorial handling and peer review process, inappropriate or irrelevant references or not being in scope of the journal or guest-edited issue. Based on the investigation's findings the Editor-in- Chief therefore no longer has confidence in the results and conclusions of this article. The author M. Durga Prakash disagrees with the retraction. The authors Siva Sankara Phani Tammireddy, Mamatha Samson, P. Rahul Reddy, A. Kishore Reddy, Asisa Kumar Panigrahy and Sudharsan Jayabalan have not responded to correspondence regarding this retraction.The online version of this article contains the full text of the retracted article as Supplementary Information.

Medical diagnosis has been developed with new techniques which are capable of performing very sensitive detection and quantifying certain parameters. Microfluidic based sensors are taking very essential part in the diagnosis of several parameters. These parameters can be correlated with the presence of specific molecules and their quantities. A lab-on-chip biosensor is a miniaturized device integrated in a single chip which can perform one or several analyses including human diagnostics done in the laboratory. This work presents, design and model of a lab on chip biosensor with molecule parameters using COMSOL multi-physics. In this paper, designed a glucose sensor, which can be used to track the glucose levels in body which helps diabetic patients maintain their glucose levels. The aim of this work is to design of a glucose sensor which is highly sensitive. The sensor is designed with an electrode and reaction surface in a micro channel. The designed sensor harvests a decent sensitivity in terms of average current density and with a limit-of-detection value 0.01µM.

Biomedical applications adapt Nano technology-based transistors as a key component in the biosensors for diagnosing life threatening diseases like Covid-19, Acute myocardial infarction (AMI), etc. The proposed work introduces a new biosensor, based on Graphene Field Effect Transistor (GFET), which is used in the diagnosis of Myoglobin (Mb) in human blood. Graphene-based biosensors are faster, more precise, stronger, and more trustworthy. A GFET is created in this study for the detection of myoglobin biomarker at various low concentrations. Because graphene is sensitive to a variety of biomarker materials, it can be employed as a gate material. When constructed Graphene FET is applied to myoglobin antigens, it has a significant response. The detection level for myoglobin is roughly 30 fg/ml, which is quite high. The electrical behavior of the GFET-based biosensor in detecting myoglobin marker is ideal for Lab-on-Chip platforms and Cardiac Point-of-Care Diagnosis.

In this paper, we propose a novel “Teeth Junctionless Gate All Around Field Effect Transistor” (TH-JLGAA FET) based on gate engineering method, to obtain finer electrical characteristics. A 3 nm TH-JLGAA FET is designed and was scaled up to 14 nm to observe the effect of scaling on device performance. The characteristics are revealed and compared with contemporary JLGAA FETs. The results show that the novel TH-JLGAA FET appears to have finer Sub-thresholdSlope (SS), Drain Induced Barrier Lowering (DIBL), transconductance (gm), Ion/Ioff current ratio and threshold voltage roll-off. Moreover, these remarkable characteristics can be controlled by engineering the structure and volume of the gate. In addition, the sensitivities of the novel TH-JLGAA FET device with respect to structural parameters are probed.

This study evolves an ultrasensitive label free electrical device, the silicon nanowire field effect transistor (SiNW FET) for cardiac troponin I (cTnI) in acute myocardial infarction (AMI). In this work, SiNW FET is designed, simulated using COMSOL semiconductor module to identify the presence of different concentrations of cTnI present in human blood. The surface of the SiNW is functionalized with the cTnI monoclonal antibody (mAb-cTnI) on attached to detect cTnI antigen. The response of the device is also studied using cTnI at different concentrations with the lowest limit of detection of 0.002 ng/mL. The presented SiNW FET in this study shows considerable response than the earlier developed devices and signify impressive capability for subsequent implementation in point-of-care (PoC) detection.

The physical modelling of the tunnel field effect transistor (TFET) is done in this study. The Silvaco TCAD tool is used to design and simulate the TFET structure. The FET device has attracted a lot of attention as the ideal tool in creating biosensors because of its appealing properties such as ultra-sensitivity, selectivity, low cost, and real-time detection capabilities in sensing point of view. These devices have a lot of potential as a platform for detecting biomolecules. Short channel effects, specificity, and nano-cavity filling have all been improved in FET-based biosensors. FET-based biosensors are appropriate for label-free applications. Random dopant variations and a thermal budget are seen during the construction of a JLFET. To overcome this problem, the charge-plasma-based concept was established in FETs in this study. Different metallurgical functions for electrodes were employed in this biosensor to behave as a p-type source and n-type drain. To alleviate the short channel effects, a dual material gate work function for the gate electrode was devised, as well as a double gate architecture. Biomolecules can be neutral or charge-based, and both types of biomolecules can be identified using a proof-of-concept FET-based biosensor. Changes in the drain current (Id) of the device were achieved by varying dielectric values and charges in the cavity region with variable cavity lengths.

Ion Sensitive Field Effect Transistors (ISFET) are most widely used in medical applications due to simple integration process, measurement of sensitivity and its dual properties. These ISFETs are originated from Metal Oxide Semiconductor Field Effect Transistors (MOSFET) with improvements in structure. ISFETs are used as bio-sensors for the detection of biomarkers in blood, DNA replication and several other medical applications. In this article, we design the ISFET pH sensor in two dimensions with integration of two models namely, semiconductor model and electrolyte model are represented using manageable global equations. The sensitivity of ISFET with different oxide layers is measured and compared. We also measure the sensitivity of the designed 2D-ISFET in two different solutions and compare it with different oxides to know the best oxide material to be used to design the device.

The most affected disease in recent years is Severe Acute Respiratory Syndrome Coronavirus 2 (SARS-COV-2) that is notable as COVID-19. It has been started as a disease in one place and arisen as a pandemic throughout the world. A serious health problem is developed in the lungs due to the effect of this coronavirus. Sometimes it may result in death as a consequence of extensive alveolar damage and progressive respiratory failure. Hence, early detection and appropriate diagnosis of corona virus in patient’s body is very essential to save the lives of affected patients This work evolves a Silicon (Si) based label-free electrical device i.e. the reduced graphene oxide field-effect transistor (rGO FET) for SARS-CoV-2 detection. Firstly rGO FET functionalized with SARS-CoV-2 monoclonal antibodies (mAbs). Then the rGO FET characteristic response is observed to detect the antibody-antigen reaction of SARS-CoV-2 with different molar ranges. The developed GFET shows better performance towards the drain current and limit-of-detection (LoD) up to 2E-18 M. Therefore, we believe that an intense response was observed than the earlier developed devices and signifies impressive capability for subsequent implementation in point-of-care (PoC) diagnostic tests.

In this paper, gate oxide overlapping technique is implemented in heterojunctions to obtain better subthreshold swing, high ON state current and improved miller capacitance for beyond-CMOS technologies. Inter band tunneling (BTBT) of hetero-transistor is increased which in turn causes ON-OFF state current ratio increased, on other hand standby current decreases. Low bandgap materials such as Ge or GeSi materials are used in the fabrication process for better performance in the device level of abstraction. The low voltage operation of HETT in subthreshold region is very useful for power-efficient memory applications. This work also demonstrates the device level variations between HETT and traditional MOSFET in detail. The N-type heterojunction (NHETT) with gate oxide overlap is designed and implemented. The subthreshold swing of 16 mV/dec at operating supply voltage 1.2 V is obtained. The improved Miller capacitance can be obtained because of oxide overlap and low band gap materials.

Due to various kind of Band-To-Band Tunneling (BTBT) operation, Heterojunction Tunnel Field Effect Transistors (HEFETs) are widely used in ultralow power applications. Anyhow, circuit complexity is a major issue in case of HEFET based memory development because of their uncomfortable size. Device scaling is a better way to eliminate such kind of issues for HEFET based memory development. Thus, development of Gate-oxide Overlapped Source-HEFET (GOS-HEFET) with lower Subthreshold Swing (SS) based Silicon on Insulator (SOI) is proposed to achieve perfect scaling in this work. Tunneling operation is done with the help of Si-based tunnel devices which are considerably lower than that of MOSFETs. Tunneling rate is enhanced by small bandgap material (Germanium (Ge)) in the source (S) while the ambipolar leakage is minimized by wide band gap material (Silicon (Si)) in the channel. Here, Ge is mainly utilized to dope the source region of P type transistor while Si is used to dope the drain (D) region of N type transistor. Moreover, the tunneling rate of BTBT is enhanced by the geometric alignment of the P and N type transistors with the gate oxide/semiconductor interface. Based on this procedure, five different kinds of SRAM (6 T, 7 T, 8 T, 9 T and 10 T) memory cells are designed. The proposed GOS-HEFET with lower SS on SOI design is implemented using SILVACO TCAD and TANNER CMOS technology. Then, power performance for different temperatures of the proposed method is compared with conventional HEFET based SRAM memory cells.

3D IC Integration shows the most emerging technology for future integration nodes which is now a most important trend for the semiconductor industries. Through-silicon-via (TSV) based integration is the prime technique to facilitate 3D IC integration without compromising the Moore's law. It is likely to usher the IC industries a paradigm shift from planar integration as it provides major benefits like improvement of system performance, power and enables heterogeneous integration. In this paper, we report Germanium/poly-germanium as an substitute material for Silicon/poly-silicon due to its superior carrier mobility. Mobility of electrons and holes in c-Silicon is 1500 cm2/V-s and 450 cm2/V-s respectively, where as in c-Germanium, the respective values are 3900 cm2/V-s and 1900 cm2/V-s. Therefore, considering these carrier mobility values we can envisage that poly germanium will be one of the ideal candidate towards realizing a high speed TSV interconnect when compared with poly-silicon. Nevertheless, even though copper is used widely to fill TSVs, it is also bereft of proper thermal expansion match with Silicon/dielectric (SiO2). The coefficient of thermal expansion (CTE) of Cu (~17.5x 10-6 /°C) is many times more than of silicon (~2.5x 10-6/°C). Hence, there will be heavy mismatch between Cu filled TSV and Silicon/SiO2, and then it creates stress and strain between the interfaces. The CTE of germanium (5.8x 10-6/°C) is very close to Silicon, thus there CTE mismatch is very less, this fact is also an added advantage for Germanium to challenge copper as TSV material.

This paper presents a comprehensive survey on the recent developments in Graphene Field Effect Transistor (G-FET), considering various aspects such as fabrication, modelling and simulation tools and applications especially in sensors, highlighting the future directions. Complying with the Moore's law, to increase the transistor density of an Integrated Circuit, new alternate materials for fabrication have been tried, instead of silicon due to its limitations in reducing transistor dimensions. Graphene, one such material, proves to be a suitable alternate for silicon due to the factors like superior carrier mobility and very high trans-conductance gain, etc and G-FET is becoming the most suitable choice for high-speed analog VLSI, RF, and bio- sensor circuits.

Emojis are a small visual representation of emotions or objects that are usually used in text messages to enhance the communication experience between individuals. With the rise in the widespread use of social media platforms like Twitter and instant messaging, many users are using these emojis in their text messages to convey broad feelings efficiently, which sometimes cannot be expressed using just words. This combination of text and emojis to improve emotion has become an essential part of how people communicate in the 21st century. Thus, giving rise to a problem statement that is to identify the relationship between these text messages and the emojis used in them. In this paper, we propose an approach to predict multiple emojis for a given text-based tweet message. Our proposal contains three modules, where the first module preprocesses the given text data, the second module is the model on which the data is trained, and a multi-class classifier to predict the emojis evoked by the given text. The objective of this model is to understand the underlying semantics of the text sentence using natural language processing techniques to predict reasonable emojis.

This paper admits a low-noise amplifier (LNA) designed by taking bio-medical applications into considerations. The amplifier is designed based on two gain stages, supply insensitive gain stage and inverter gain stage. Input-referred noise of the proposed amplifier is 18.02 mVrms and it consumes a power of 0.012 mW. The amplifier produces a gain of 86.5 dB. Bandwidth of the proposed amplifier is 227 Hz with cut-off frequencies as 227 Hz (higher) and 1 MHz (lower). The entire system is built in 45 nm technology with supply voltage of 0.6 V.

The device scaling restricted due to the limitation of the subthreshold swing of the MOS transistor, which is not less than 60 mV/dec. The researchers are concentrating more on power efficient techniques for advanced, more featured, electronic systems. In place of MOS transistor, which is homojunction, if a heterojunction transistor with low bandgap materials used, the subthreshold swing of the transistor being reduce to below 60 mV/decade and low leakage current can obtain. Ge, GeSi, etc. materials are used in the design and implementation Heterojunction Tunneling Transistor (HETT) due to low band gap. In this work, both types of HETTs such as NHETT and PHETT designed and implemented using low bandgap materials with a technique of increasing tunneling area by overlapping. The performance of NHETT and PHETT described by the design and implementation of 7T MOSFET SRAM. The power and delay analysis of this SRAM cell using HETTs presented, and the results compared with MOSFET based standard 6T, conventional 7T SRAM cells.

With demand for high performance and huge logic dense portable devices, the need for silicon area is increasing. A potential solution for the electronics industry to develop such huge logic demanding applications is the ability to reconfigure the system partially without altering the overall system operation. For more than two decades, reconfigurable computing has aided various applications and has seen tremendous technology transformation. The paper presents a survey of reconfigurable computing, its present state of existence, and a detailed report on state of art Partial Dynamic Reconfiguration Framework (PDRF) for reconfiguring FPGA designs partially and dynamically. A detailed analysis of the features, limitations, and performance of a wide range of PDRFs available in the literature are reported.

Early detection of diseases became a big task for early medication. To detect these diseases, sensors with antibody-antigen combinations play important role. From the past several years, one of the prominent sensor structures to obtain the requirement consists of Silicon nanowire. The major impact of Silicon Nanowire Field Effect Transistor (Si-NW FET) structures respond to small change in the gate length and type of silicon material concentration as a gate material. Si-NW material in the range of nano regime, because of their property gate has higher surface to volume ratio. Hence, high surface to volume ratio of Si-NW FETs results better performance for the various sensing applications. For obtaining high surface to volume ratio is challenging due to high in fabrication cost and design constrains. In this paper presents to optimization and improve the performance of Si-NW FET with altering different parameters like gate length and doping concentrations of silicon material. The device is simulated using TCAD software with different gate length and type silicon materials with phosphorous (n-type) and boron (p-type) doping concentrations performance are obtained with drain current (Ids) and compares all the obtained resistivity values and that leads to the better performance of the device.

In this work, the concept of hybrid structured channel is proposed to reduce the short channel effect (SCE), while still permitting high current through the channel. 5nm Dual gate junctionless gate-all-around (JL-GAA) FET using two different hybrid structured channels (i.e. concentric cylindrical and zigzag structures) were compared. The performance characteristics of the two hybrid structures were attained and analyzed. The zigzag structured channel showed to have higher conductivity, constant Dirac point, high output conductance of ~220% more than concentric cylindrical structured channel.

The low voltage operation is one of the best techniques for ultra-low power portable, embedded mobile systems. This can be obtained by scaling of the devices in CMOS technology. But, it is very difficult to operate the system below a certain operating voltage due limited subthreshold swing of MOSFET which is not less than 60mV/decade. The ultra-low power battery powered portable systems need better replacement for MOS device. One of the best alternatives for this problem is to replace the transistor itself with a reduced subthreshold swing device such as heterojunction transistor called HETTs (Heterojunction Tunnel Transistors. High ON state current, Lower subthreshold swing, Improved Miller capacitance, low leakage current and lower power consumption are the advantages of HETT over MOSFET.Low voltage operation and scaling of the transistor is also possible. Low bandgap material based HETTs are best choice of portable systems memories. In this paper, low bandgap material based NHETT and PHETT are designed, implemented and fabricated. Using these HETTs, different SRAM configurations such as 6T, 7T and 8T SRAM cells designed and implemented. The power and delay of these designs are obtained and validated with MOSFETs.The physical and electrical differences between MOSFET and HETT are elaborated in detail.

The battery-powered mobile devices limited energy process by MOSFET's due to subthreshold swing and underneath 60mV/dec for ultra fewer energy applications. This research introduces the layout and execution of a mobile electronic device full-on-presence, extended Miller potential, and reduced HETT subthreshold swing effectiveness has been compared with MOSFET's Gate oxide blending on source can increase channel tunneling in this work. To enhance transistor line, Miller capacitance impact can be decreased by using low band offset equipment and small power product of metals such as Ge or SiGe. This, in turn, leads to stronger transistor efficiency features. The proposed layout and execution of HETT includes manufacturing of mutually NHETT and PHETT and efficiency analyzes of both NHETT and PHETT. Concerning the fundamental and skeletal distinctions among MOSFET and HETT to promote the utilization of MOSFET instead of HETT, the benefits and constraints of both NHETT and PHETT have been detailed. HETT's construction process is by no means entirely different, suitable for the scheme of MOS method and suitable for transportable motorized applications. HETT provides the 6T SRAM cell electricity evaluation and the output was reviewed using standard SRAM cell. The average power, maximum power and minimum power of SRAM by using both MOSFET and HETT are obtained and compared. The mask layers of HETT fabrication is not that much difference than MOSFET and hence CMOS MOSFET fabrication is friendly to HETT fabrication. In future, the combination of both CMOS MOSFET and HETT are used, CMOS technology for digital logic and HETT for semiconductor memory applications.

An era of accelerated technological progress characterized by innovations whose rapid application caused abrupt changes in the electronics industry for the past eight decades. Due to these advancements in the technology, there is a solemn drift towards the portable electronic systems in human life. These systems consist of adders, multiplexers, registers, memories. The major stumbling block of these portable mobile systems is the amount of power consumption. Memories are more power consuming components in embedded applications. To avoid the frequent charging of the batteries embedded systems should be equipped with large battery sources. The capacity of the battery depends on the power consumption of the system. The higher the power consumption, the higher is the battery capacity which is unacceptable for portable embedded systems. So, for better performance of integrated systems, we need effective low power VLSI techniques. Many authors proposed low power techniques for design and implementation of the systems, but the low voltage operation is the most effective energy saving method. Low power and ultra-low power applications for different heterojunction tunneling architectures have been analyzed and presented in this paper. Analysis of heterojunction architectures can be done with ION/IOFF ratio, leakage current, subthreshold swing (SS) and materials used for manufacturing and the trade-off between these parameters is required. Therefore, the proposed architecture addresses high ION/IOFF ratio, steeper subthreshold swing and improved Miller capacitance with less leakage current. These structures thereby enhance the performance of the heterojunction architectures.

�Abstract: This paper admits a LNA (low noise amplifier) designed by taking bio-medical applications in to considerations. The amplifier is designed based on two gain stages, supply insensitive gain stage and inverter gain stage. Input-referred noise of the proposed amplifier is 18.02 mVrms and it consumes a power of 0.012 mW. The amplifier produces a gain of 86.5 dB. Bandwidth of the proposed amplifier is 227 Hz with cut-off frequencies as 227 Hz (higher) and 1 mHz (lower). The entire system is built in 45-nm technology with supply voltage of 0.6 V.

Read and write battle and scaling limitations in standard 6T SRAM, the insufficient subthreshold performance of conventional 7T SRAM and more standby power of 8T SRAM demand the researchers o develop more stability, energy efficient, high speed and better performance memories for market demand. Low power subthreshold region operated 7T and 8T with read assist SRAMs are designed and implemented at an operating voltage of 0.1V. A grounded gate terminal of the cross-coupled inverter of the memory unit increases the stability and performance during the read as well as in write operations with reduced power consumption and delay. Nevertheless, the number of the transistors increased, the proposed designs reduce the power and delay with ground shorted gate terminal in one of the inverters of memory unit. The power and input to out delay of the proposed memory cells analyzed and elaborated with reference standard 6T, conventional 7T, and conventional 8T SRAM cells.

Static Random Access Memory is a type of semiconductor memory that uses bi-stable latching circuitry (flip-flops) to store each bit. SRAM exhibits data reminisce but it is still volatile in the conventional sense that data is eventually lost when the memory is not powered. The power consumption of SRAM varies widely depending on how frequently it is accessed. Several techniques have been proposed to manage power consumption of SRAM-based memory structures. A typical SRAM cell is made up of six MOSFETs.SRAM plays a substantial role in the world of microprocessors. As the world is craving for devices that are compact and portable, there is a need to reduce the size of SRAM that comprises about 70% of the SOC (System on Chip). Scaling is the one of the best techniques used in CMOS IC technology. While scaling down of the CMOS circuits, there arises a problem of high leakage losses. For solving this problem in SRAM cells, a transmission gate based 8T SRAM cell is used. The 8T SRAM cell is analogous to the 6T SRAM cell, the only exception being the 8T SRAM cell possesses full transmission gates which replace access pass transistors. In this work, the transmission gate based 8T SRAM cell to minimize the power consumption and losses is designed and implemented by using Heterojunction Tunnel Transistors (HETT) and the performance analysis is done with reference to conventional transmission gate based 8T SRAM Cell.

Subthreshold Swing (SS) of MOSFETs, which determines the low voltage operation of portable mobile devices, cannot reduce below 60mV/dec that restricts MOSFETs for ultra-low power applications. This work presents design and implementation of high ON current, improved Miller capacitance and reduced Subthreshold Swing heterojunction tunneling transistors (HETTs) for portable electronic systems. The performance of HETT with MOSFET has been compared. In this work, the overlapping of gate/oxide on to source can increase the band to band tunneling (BTBT) and improves the ON current of the transistor. Miller capacitance effect can be reduced by the use of low band offset materials and low energy states of materials like Ge or SiGe. This, in turn, results in better performance characteristics for the transistor. The Proposed design and implementation of HETT include both N-type HETT (NHETT) and P-type HETT (PHETT) fabrications and the performance characteristics analysis of both NHETT and PHETT are provided. The advantages and limitations of both NHETT and PHETT for beyond CMOS technologies, in addition to the basic and structural differences between HETTs and conventional MOSFETs to facilitate the use of HETT in place of MOSFET have been elaborated in detail. The construction process of HETT is not at all completely different which is suitable to MOS Design process and is applicable for portable mobile applications. The power analysis of HETT based standard 6T SRAM cell is provided and the performance is verified with the conventional MOSFET based 6T SRAM cell.

Present-day technology has reached a goal where an entire system can be implemented on a single chip which is nothing but called system on chip (SOC). It involves microcontrollers and various peripheral devices with each peripheral device having its own intellectual property (IP) named as IP cores. Serial communication is established between these IP cores using various protocols like RS232, RS422 and UART etc. They perform point to point communication which requires huge wiring connections, multiplexing of all the bus connections to deliver the information to the IP Cores. To overcome this I2C protocol is developed by Philips, which is a two line communication. Here only two pins, i.e., SCL and SDA establish connection between various devices considering one as master and other as slave (Eswari et al. in Implementation of I2C Master Bus Controller on FPGA, 2013) [1]. These two pins communicate using particular commands like start, address, read/write, acknowledgement and stop commands. These commands show a particular format in which data should transfer. Both 7-bit and 10-bit addressing formats can be used, 10-bit addressing supports more addressing lines, i.e., 1024 compared to 127 addressing lines in 7-bit mode. The advantage in this protocol is it has low wiring data transfer rate that can be improved using Ultra-Fast mode (UFm) (Bandopadhyay in Designing with Xilinx FPGAs. Springer, Switzerland, 2017) [2]. Ultra-Fast mode is a unidirectional data transfer mode, i.e., only writing data to an address can be done. In this paper they perform verification for the design of an I2C protocol between a master and a slave using system Verilog and UVM in the tool SimVision.

Today’s scenario of semiconductor technology is a tremendous innovation; it includes a large number of intellectual property (IP) cores, interconnects, or buses in system on chip (SOC) design and based upon the necessity its complexity keeps on increasing. Hence, for the communication between these IP cores, a standard protocol is developed. The necessity of IP reuse, abridging the design time and the complexity makes large-scale SOC more challenging in order to endorse IP core reusability for SOC designs. An efficient non-proprietary protocol for communication between IP cores is open core protocol (OCP). OCP comes under socket-based interface and openly licensed core concentric protocol. This paper addresses on the verification of implemented design of OCP. The proposed paper is to verify the implemented design by using System Verilog and Universal Verification Methodology (UVM) in SimVision tool.

The file depicts the arrangement, utilization and affirmation of a framework on chip bound to execute the MAC convention of a body region categorize immense with the IEEE 802.15.3 standard. Accelerating of MAC convention exercises is refined through a specific hardware/programming allocation. However, the MAC convention animating operator, a blast is realized on the chip to have the framework’s firmware. The report closes by displaying the rule characteristics of the framework - on-chip executed.

In the last few decay, Network on Chip's (NoC) are the powerful chips for high speed communications pertaining to 802.11 Ethernet protocol which is a need to be reconfigurable for successful data frame transmission. The existing architectures like coarse grained reconfigurable, ALU cluster and expression grain reconfigurable architecture and look-up-table used in fine grained reconfigurable devices requires a lot of storage memory, hardware resources such as slices, cell area and cell delay. To tackle these issues, Multigrained Reconfiguration and Parallel Mapping Architecture (MRPMA) is proposed and their performance analysis parameters are calculated. The MRPMA uses the four contributions to optimize Processing Elements (PE's) operations: 1) Fast Fourier Transformation (FFT) to perform fixed point numbers to the configuration words, 2) Discrete Cosine Transformation (DCT) to analyze the data in the frequency domain, 3) Finite Impulse Response (FIR) for parallel mapping the data and 4) Channel encoder and decoder to encode the data and to calculate the shortest route from source to destination switch.

Today's scenario of semiconductor technology is a tremendous innovation, System on chip (SOC) design is of a great number of Intellectual property (IP) Cores which requires an efficient protocol for all types of operations. Large scale SOC gets more demanding due to the unavoidable importance for IP reuse, complexity and abridging the design time while encouraging IP core reusability for SOC designs. Extended modes of a non-proprietary protocol like Open core protocol (OCP) are more efficient. OCP comes under socket based interface and openly licensed core concentric protocol. This paper addresses on the verification of implemented design of Extended OCP. The proposed paper is to verify the implemented design by using System Verilog and Universal Verification Methodology (UVM) in SimVision tool.

Present day's technology has reached a goal where an entire system can be implemented on a single chip which is nothing but called system on chip (SOC). It involves microcontrollers and various peripheral devices with each peripheral device having its own intellectual property (IP) named as IP cores. Serial Communication is established between these IP cores using various protocols like RS232, RS422 and UART etc. These protocols perform point to point communication which requires huge wiring connections, multiplexing of all the bus connections to deliver the information to the IP Cores. To overcome this I2C protocol is developed by Philips, which is a two line communication. Here only two pins i.e., SCL, SDA establish connection between various devices considering one as master and other as slave, as in [1]. These two pins communicate using particular commands like start, address, read/write, acknowledgement and stop commands. Both 7-bit and 10-bit addressing formats can be used, 10-bit addressing supports more addressing lines i.e., 1024 compared to 127 addressing lines in 7bit mode. Clock stretching case is explained here clearly i.e., when a slave needs to have control on the clock generated by the master. The advantage in this protocol is it has low wiring; data transfer rate can be improved using Ultra-Fast mode (UFm), as in [2]. In this paper they perform verification for the design of an I2C protocol between a master and a slave using system Verilog and UVM in the tool SimVision.

This paper mainly discuss the aspects in the design and simulation of rectangular cantilever and circular disk micro strip transmission line based capacitive RF MEMS switches. In both the designs the structure is placed on a silicon dioxide (SiO2) dielectric material with dielectric constant of 4.5 and the thickness of 1μm. Here an analysis is done by taking different metals (Al, Au, Cr, Cu, Pd, PT, Ti, W) of thickness 1μm as structural material and observed the deformation, capacitance variations, and switching time. It is good for aluminum metal as a Micro-strip material. And compared to circular disk structure, rectangular cantilever is giving good performance of better displacement of 0.9μm and capacitance variation of 0pF-5.5pF for the actuation voltage of 2.55 V. This paper extended the analysis by extracting the lumped circuit for the microstip transmission line based RF MEMS Switch, after doing the lumped analysis, it is proved that aluminum based cantilever structure exhibiting negligible losses of 0.1dB.

In this paper we demonstrate synthesis and characterization of MWCNTs embedded SU-8 electrospun nanofibers and their application towards ultrasensitive detection of cardiac biomarkers using Electrochemical Impedance spectroscopy (EIS). The composite nanofibers have excellent electrical and transduction properties owing to the presence of MWCNTs in addition to ease of functionalization and biocompatibility, which can be attributed to the presence of SU-8. Thus the synthesized nanofibers are ideal candidates for sensitive biosensor applications. As a proof concept, the detection of cardiac biomarkers, Myoglobin (Myo), cardiac Troponin I (cTn I) and Creatine Kinase MB (CK-MB) is demonstrated. The synthesized nanofibers were functionalized with the antibodies of the biomarkers and the detection was carried using Electrochemical Impedance Spectroscopy, an excellent technique for understanding the adsorption kinetics. A minimum detection limit of nano-gram/ml is demonstrated using this nanobiosensor platform.

This paper is used to understand the design and structure of a nonvolatile memory cell. Charge injection was improved by reducing the effective oxide thickness of the gate dielectric. Metal/ Al2O3/SiN/SiO2/Si structure was designed to determine the charge trapping properties. High programming and erasing speed as well as large shift of the threshold voltage with high endurance were obtained by scaled down dimensions.

This paper reports the synthesis and fabrication of aligned electrospun nanofibers derived out of multiwalled carbon nanotubes (MWCNTs) embedded SU-8 photoresist, which are targeted towards ultrasensitive biosensor applications. The ultrasensitivity (detection in the range of fg/mL) and the specificity of these biosensors were achieved by complementing the inherent advantages of MWCNTs such as high surface to volume ratio and excellent electrical and transduction properties with the ease of surface functionalization of SU-8. The electrospinning process was optimized to precisely align nanofibers in between two electrodes of a copper microelectrode array. MWCNTs not only enhance the conductivity of SU-8 nanofibers but also act as transduction elements. In this paper, MWCNTs were embedded way beyond the percolation threshold and the optimum percentage loading of MWCNTs for maximizing the conductivity of nanofibers was figured out experimentally. As a proof of concept, the detection of myoglobin, an important biomarker for on-set of Acute Myocardial Infection (AMI) has been demonstrated by functionalizing the nanofibers with anti-myoglobin antibodies and carrying out detection using a chemiresistive method. This simple and robust device yielded a detection limit of 6 fg/mL.

The present work demonstrates ultrasensitive, label free biosensor platform using Self Assembled Monolayer (SAM) modified Electrospun ZnO nanofibers. The inherent sensing ability of ZnO nanofibers is enhanced by modifying the fibers with 3-mercaptopropionic (MPA) acid. This role of MPA is to generate carboxylic acid (-COOH) group which can easily be functionalized with any protein molecule by a simple, well established crosslinking biochemistry. To synthesize the nanofibers electrospinning technique, a simple, low cost, robust technique, was utilized. The as-synthesized ZnO nanowires were characterized using Field emission-scanning electron microscopy (FE-SEM), Energy dispersive X-ray spectroscopy (EDX), X-ray diffraction (XRD). The performance of sensor was verified with standard Biotin-Streptavidin interaction as model system using Cyclic Voltammetry (CV). The sensor exhibits excellent sensitivity (613 μ?/mg ml-1/cm2) within 1 μgml-1-1fgml-1 of streptavidin with lfgml-1 lower detection limit.